AM Modulation with PXIe 5641R

[edbetita]

Hi

I've been working on my thesis wherein we have to develop an RFID Reader that can test the compliance of UHF Passive Tags. I've been working on the modulation schemes for a while now. I have to develop the DSB-ASK and SSB-ASK modulation schemes.

At first I used the ASK Modulator but I immediately replaced it with an Amplitude Modulation VI because I would be modulation PIE Encoded signals and not just the bit stream.

Will the AM VI work with the FPGA Module? If not, I'm planning to recreate the block diagram for DSB and SSB generation instead. Is there a way I can recreate the sinus at the IF frequency to be multiplied with the message to create the modulated waveform? I've been at this for a while. Hope you can help me. Thanks!

[Elizabeth_K.]

Hi edbetita,

Can you explain a bit more of why you would like to push the AM modulation onto the FPGA? Also, I'm not 100% sure which VI you are referring to, is it the Amplitude Modulation VI in the Modulation Toolkit? If so, it will not work on the FPGA, because floating point is not supported in LabVIEW FPGA.

I would also like to point you to the LabVIEW FPGA RF Communications Library, which may be useful for your project.

- Elizabeth K.

[edbetita]

Hi. Thank you for your reply and for your reference to the FPGA Communications Library. 

I've attached an image of what I'm supposed to be doing in the FPGA.

The message is the bitsream that we would be modulating that is encoded using a Pulse Interval Encoder. The output of that encoder is the one that we need to modulate with an IF carrier of 25MHz. 

Okay. I had an idea. 

By the way, is the phase shift method for SSB generation possible to be realized on the FPGA? thanks!

[Lars.B]

AM on the IFRIO is really simple: Just hold Q-part at 0 and modulate then your carrier with I-part. 100% modulation grade := FSR of DAC (here: 14bit).

But as you see, AM doesn't help you to get SSB.... actually I am missing how to suppress the carrier.

[edbetita]

Hi! Thanks for your reply!

I figured the AM part by  reading the other posts here. Thanks for confirming it! 🙂

About the SSB modulation, I'm at a lost too on how to do it since the DAC is responsible for generating the modulated signal at the IF frequency. I have no clue how to work on the signal after the DAC. 

Will it help if I mention that I will be integrating it using a PXI 5610 upconverter? I'm using it to upconvert my signal to RF. I've been tinkering on its RF configurations but I haven't found something relevant yet or perhaps I am missing out on something.

Thanks in advance for your help on this!

[Lars.B]

Hi!

The upconverter is well known to me - in just that configuration with IFRIO (PXIe-5641R). In the past I've used it to implement the RF-interface in a communication tester for e.g. car keys (if your are able to read german and interested: ftp://ftp.ni.com/pub/branches/germany/vipdays_09_sessions/pruefstand_3_schmitz_huber_sea_datentechni... ).

The upconverter isn't able to modify anything on the signal, except maybe bandwidth and purity. 😉 It does just what the name says: converts from a lower frequency to a higher one.

So, if you want to modify your signal, you have to do it on IFRIO/FPGA-level before it passed the DAC. One way would be to implement SSB on FPGA-level, so it is interpreted in I/Q-manner (as AM mentioned before) - one other way would be to use modulation toolkit on host-level and stream I/Q-data to FPGA. But... Second way is not suitable to your application as I understand (because of timing matters).

AM/FM/PM (... or it's digital conterparts ASK/FSK/PSK) are no problem to me, I am using them - SSB don't and actually I don't know how to build them as I/Q-data. Have you tried to find such a description?

Btw, and more in general, to your question with sinus on FPGA: Instead of multiplying with sinus in most cases multiplying with rectangular data is also suitable. And that is just a counter which toggles your signal (respectively toggeling the sign) with the desired frequency.

Greets

Lars

[Lars.B]

Additionally: Do you know https://decibel.ni.com/content/docs/DOC-4068 ?

It's sometimes very helpful at beginning point.

[edbetita]

Hi. I attached the block diagram for the generation of the SSB signal. I will try this on the FPGA side first.

IOs it right to suppress the Q part of my data at the host part? I've also attached a part of my code here. This is from the HOST side. For now the FPGA is only used for transmitting the I and Q data. I just scaled the gain of the I at the host part.

Sorry for the trouble. 🙂

[Lars.B]

Well well, assuming the box labeled "DSB-SC" is meant as multiplicator, the diagramm in picture ssb.jpg makes sense.

In the upper path (I) an AM-signal is generated.

In the lower path (Q) also, but with an delay of 90°. In other words: the generated signals will extinguish after adding, with exception of one sideband-signal. Which one you could decide with the sign of  your signal feed into Q-part.

To mention: All you have to implement is the both ways from "Analog signal" upto the boxes "DSB-SC" - all other is already fixed in HW (I/Q-modulator).

##

A very similar way I've used in the past to generate FSK, with user defineable shift frequencies (which is in my code, in fact, SSB with fixed tones). Just forgotten and not longer thought about that...

There all you need are a sine (feed to I) and cosine (feed to Q) -> cosine = 90° delay

[edbetita]

Hi! I've implemented the block diagrams of SSb and DSB AM Modulation at the host. I used a square wave instead of the encoded signals just for simulation purposes. I've been trying to view the transmitted signal using an oscilloscope but somehow I can't generate it at all. I've tried the Single Tone example for the 5641R and we are able to view it just fine. 

Do you have any insights on this.

Also, we have received a 'timing violation' the last time we compiled the FPGA. We resolved it by setting the DAC_1_TxEnable to False, It compiled but our code isn't running the way we think it should. I hope you could help us on this matter. Thanks! 🙂