how do you increase the FPGA data clock?

[emonk]

I'm using LV 14 and USRP 14.5.  When I plug in my new USRP-2940R-120 and run a program written for a USRP-2940R-40, the driver gives me a message that says "You are using a bitfile configured for a data clock that is slower than the rate required for the bandwidth of this device. This may result in aliasing in your signal." (error 1073383043). 

Fair enough. 

Then I looked at the data clock properties in the application project and found that I could not change any of the values in there.  So...how do I change the FPGA data clock rate and what should I change it to?

Thanks.

[DylanDylanDylan · Accepted solution]

Hi emonk,

We created a new FPGA target which samples at 200 MS/s to utilize the increased BW. You will need to recompile your application using the new target. My recommendation on the easiest way to do this is as follows:

1. Generate a new sample project. With NI-USRP 14.5 all sample projects now have both targets (120 MSps and 200 MSps)

2. Did you customize the FPGA in your application? If not all you need to do is use the bitfile for the 200 MS/s target from the sample project in your host code. If you did, you will need to redo those customizations in the top level FPGA VI of the new target. This can be either trival or difficult depending on your application,

3. You will then need to recompile. Due to the faster clock rate, meeting timing is more difficult so your FPGA IP may need to be optimized if you are running in the data clock domain. I suggest kicking off 5-10 compiles at first due to the variabiliy in each compile. If all still fail, use the timing reports to investigate where optimizations are needed.

Let me know if you have any questions or run into issues.

[whiteweak]

Hi emonk

               I meet the same error，how did you solved this error。Recompile as “DylanDylanDylan” say?

thanks