do IQ pairs have to be concatenated before fifo'd ?

[apchar]

I'm trying to understand the "Streaming Xcvr (FPGA).vi" vi that is in the BasicTX_BasicRX project. It's the one example that does everything on the fpga and works with the x310 (I hope.) If I understand it correctly each 16 bit IQ pair is concatenated into one 32 bit integer before being sent to a FIFO. Is there any reason I cant use 2 16 bit FIFO's? Is there any risk they might fall out of sync with each other if they are in the same timed loop ? It would certainly be easier to read.

[brooksprumo · Accepted solution]

apchar,

I'm not familiar with the BasicTX_BasicRX project, but if it's based on the USRP Simple Streaming project, then yes, you can split your IQ samples (and channels) into separate FIFOs without any coherency problems. You'll have to modify your host code to fetch from multiple FIFOs, but you won't have to worry about them "falling out of sync with eachother".