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Why is the latency of my USRP repeater 550 nsec?

We have an X310, aka the 2944 (ish), I'm programming it with LVFPGA to minimize latency. I have a super simple loopback test with the receiver FPGA I/O nodes tied right to the transmitter FPGA I/O nodes. The data rate is 200 MHz. Everything works as expected (out=in) & I expected a latency of a few clock cycles. Instead it is 550 nsec. Thats 110 clock cycles! Why so much & more importantly, how do I reduce it?

Thanks.

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Hi art,

 

Can you specify the latency you are describing in a little more detail? Are you referring to the latency of the time the signal takes from transmit to receive or the latency across the PCIe bus?

 

Furthermore, can you attach a screenshot of the portion of your code which you are using to benchmark the latency?

Paul C
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The former, literally the latency between the RX2 connector & the RX/TX connector as measured on a scope. The only data crossing the PCIe bus is one way, every 100 msec, to feed the graphs. The PCIe bus is not part of the loop.  The loopback is happening entirely within the USRP. Sorry I cant make a screen shot from where I am. But I just started with the example and moved the transmitters FPGA I/O node right up next to the receivers FPGA I/O node and connected them directly, an I for an I, a Q for a Q. Everything else in the example is untouched.

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Hello

 

So, if you're directly connecting the IO Nodes, then you're left with the latency of those nodes + DAC / ADC in ticks and analog delay in/out + cables.

Most of the latency would come from the DAC (DAC interpolation/pipeline delay), can be in the order of 50-100s ticks

 

You're number is not shocking to me.

 

Does that makes sense ?

 

Regards

 

 

Victor F. | Systems Engineer
Certified LabVIEW Developer | Certified TestStand Architect
National Instruments Budapest

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I've been reading the DAC (AD9146) datasheet. Most of the latency comes from the 3 filters in the chip, 2 half band filters and a sinx/x filter. But I'm using this thing in it's simplest mode (mode 0): complex baseband centered at DC with no frequency offsets, interpolation, or modulation. So at the very least I dont need need the 2 half band filters. The chip has the hooks to bypass them. How, in vivid detail, do I do so?

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Hello Art_

 

I'll not be able to provide more details than what I've said, maybe someone else will be able to help you out on this.

Still, you're left with the DAC node latency, and you'll not be able to work around it.

 

You can try going into some DAC configuration, but I'm not sure we can support you in this direction, unfortunately.

 

Nevertheless can you provide some details on the latency you need and why ?

 

Regards

Victor F. | Systems Engineer
Certified LabVIEW Developer | Certified TestStand Architect
National Instruments Budapest

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We were hoping for a latency < 50 nsec. From what I've read in the DAC datasheet it should be possible if I can write to the individual registers that will bypass the filters. Is there a generic block that will let me write to any register I want on the DAC ? I understand why that would normally be discouraged but we really need to get this number down.

Art

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Hello Art

 

Some more tips, you can try to look at the Construct DAC Initiazation.vi, here's where you'll find it when working with a USRP Streaming Sample Project. The hierarchy is almost the same for Tx/Rx Streaming (Host).vi aswell.
Capture.JPG

 

This guy is called mutliple times, first applying a DAC reset, then after some clocking configuration (lmk for ex) is done, it'll be called again

to apply the init sequence. I guess this is where you'll be able to apply some other settings (still look at the DAC docs for proper conf sequence).

Feel free to look into it to see how the configurations are formed to be properly applied via the Register Bus.

 

Again you'll still be limited by the DAC/ADC node latency, which are basically Socketed CLIPs positioned in between LV FPGA diagram and the DAC/ADC inputs/outputs.

 

I would recommand that you do not modify directly VIs delivered by drivers, in our case those in niUsrpRio Config v1 Host.lvlib.

At least make a back up of the original because if you break it, you're also breaking Examples, Samples project etc and you'll have to repair the whole driver.

 

That said, lets hope you manage to get down by tweacking the DAC!

 

Regards !

Victor F. | Systems Engineer
Certified LabVIEW Developer | Certified TestStand Architect
National Instruments Budapest

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Thanks Victor. Setting registers 1c & 1d to 01 (disabling both half band filters) in "Construct DAC Initialization.vi" shaved 200 nsec off my latency.That's a nice improvement. But still a long way from 50 nsec. Can you explain what you mean by:

"Again you'll still be limited by the DAC/ADC node latency, which are basically Socketed CLIPs positioned in between LV FPGA diagram and the DAC/ADC inputs/outputs" ?

What is a socketed CLIP?

Art

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Hello Art

 

"Again you'll still be limited by the DAC/ADC node latency, which are basically Socketed CLIPs positioned in between LV FPGA diagram and the DAC/ADC inputs/outputs" ?

This means that the DAC/ADC nodes on your FPGA diagram have inherent latencies, due to the logic that is used to interface the DAC/ADC. That's what you'll not be able

to tweak, so unfortunately you'll be left with the latencies of those guys.

What is a socketed CLIP?
A socket CLIP allows you to interface external ressources from the FPGA

 

Regards

Victor F. | Systems Engineer
Certified LabVIEW Developer | Certified TestStand Architect
National Instruments Budapest

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