Error 61206 USRP RIO

[CrazyEce91]

Hello again,

 I am trying to run the following code on the USRP 2942R. The code is suppose to do following: The host generates a sine wave then sents it to the FPGA where its amplitude is divided by two and then sent it back to the host. This worked as a charm. The next  thing I want to do is to transmit the sine wave through the usrp. In the code I have attached I just Open a USRP RIO session and set to transmit mode and close the session. When I am trying to run the code i get the following error:

Error -61206 occurred at niInstr Register Bus v0 Host.lvlib:Set Instruction FIFO Depth.vi:1980001

Possible reason(s):

LabVIEW FPGA: The configured item does not exist

What am I doing wrong.

I have attached the Host and the FPGA vis as well as the FPGA bitfile

Thanks in Advance

[Alex.W]

Hello CrazyEce91,

Could you please attach your project file?

How did you create your project, FIFO, and bitfile? Based on this error, it seems that there is a mismatch between your bitfile and FIFO in the VI which is most likely coming from how the FIFO is configured.

Regards,

[CrazyEce91]

Hello, I have attached the project file as requested. I use two FIFOs ,the fifo is used to send data from the Host to the FPGA while sample-fifo (I know that I have to work on naming the fifos) is used to send data from the FPGA to the host .As I mentioned in my previous post, the code was working smoothly until I added the USRP RIO blocks. The bitfile was created by compiling the FPGA vi.

Regards

[Alex.W · Accepted solution]

Hello CrazyEce91,

After looking over your project, and main VI configured to look at your VI, build specification, and bitfile I have identified why you are getting an error. Although you have created a FIFO for the "reg.host instruction fifo 0" under the FPGA target this FIFO is not used in the VI, so it is not included in the build specification or bitfile. This FIFO is called in the USRP RIO initialization VI from the host, and causing an error because when looking for a reference to the FIFO it is not correctly finding the FIFO.

If you start with the NI-USRP Simple Streaming Sample Project you will see that on the FPGA VI there is a required loop marked with a red box. This loop will use the FIFO and should help to resolve the error.

For your coding, I recommend starting with the NI-USRP Simple Streaming Sample Project found by clicking File>>Create Project...>>NI-USRP>>NI-USRP Simple Streaming Sample Project. This project will most likely have more functionality than you currently need, to help simplify the project I recommend removing or replacing sections of the code or at least use this project as a guide for how to configure your NI USRP project.

 Regards,

[CrazyEce91]

I just copied and pasted this section of the code you mentioned and it worked fine thanks a ton!!!