DDR3 on x310 | USR2940R

[mikecarlos]

Hi,

I am trying to use DDR3 on my USRP 2940R. I synthesized the fpga source available on Github with X310_XG option which has DDR3 interface. However on bitstream generation step there occured an error saying

[Drc 23-20] Rule violation (REQP-79) connects_REFCLK - u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200: The IDELAYCTRL REFCLK pin should be connected.

Digging into the desing I realized a few issues. 

1. As the error suggests the clk_ref_i pin of the ddr3_32bit module is left unconnected when instantiating it in x300.v.

2. The pin sys_rst is defined as ACTIVE_HIGH when you look at the MIG project file mig_xc7k410tffg900-2.prj. However in x300.v the pin is connected to an ACTIVE_LOW signal ~global_rst

3. In the MIG project file the sys_clk_i is bound to FPGA pin AE10 however when I edit the ddr3_32bit core with MIG and move through the step I see that AE10 is not one of the options for the clock input.

Has anyone succeded in XG or HG type FPGA projects? Or they are experimental and not working at the moment as mentioned in the Makefile.

Thanks

[Peter_W]

Hi Mike,

While you might get responses here the majority of the forum activity biases towards LabVIEW programming so you may have better odds to find an answer by sending your question to support@ettus.com or by working through the USRP_Users email list. I've included the sign up link for the later below, there's a lot of activity on the list to learn from as well so I'd recommend signing up whether you decide to submit your question or not.

http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

Best Regards,

Peter W.

RF PSE

[ashish.chaudhari]

Hi Mike,

The DDR3 stuff in master was in a state of flux in the last couple of weeks and could have been broken. I just pushed a bunch of changes to master yesterday that touch the DRAM code and all the images build successfully. Can you please try pulling the laster master from the FPGA repo (commit 7bee26), and try re-building? Overall the images should be functional but we are still figuring out some throughput issues with the DRAM FIFO, and that is why they are still experimental. You will run into that problem only at high TX burst rates which may cause packet drops.

Thanks for the feedback on the issues! I would agree that it seems incorrect at first glance however, the MIG does not have the level of customizability that we need so we have a collection of patches that we apply to the generated IP products so that they can work in our design. The final parameter that are passed to the MIG core are in ddr3_32bit_mig_parameters.vh and ddr3_32bit_mig_sim_parameters.vh. Also, the clock that we use as the sys_clk_i is different from the standard part pinout. If you build an image though out makefiles, all of these patches and changes are automatically applied and the final result should be correct.

Thanks,

Ashish Chaudhari

[mikecarlos]

Thanks Asish,

I could get them working. You mention packets dropping in TX. Does packets drop during RX as well? I am aiming to write samples coming at 200MSPS. I only want to write a limited amount of samples like 64K and then stop. And I do not want to use BRAMs for this since I have run out of BRAMs. Should there be any problem with this?

Thanks

[4Matted]

Mikecarlos,

I would recommend trying what Peter has already recommended and reaching out to  support@ettus.com as they may be better suited to help you with this issue and you may get a faster response.