Can the NI USRP-295xR RIO use an Ettus BasicRX front end for IF-sampling? And what is the data rate from ADC's to FPGA?

[Idara]

Hi!

I am on the quest of replacing the somewhat ageing PCI-5640R. I'm currently using it as a portable data-log solution, mounted in a Magma Expresscard to PCI box together with a laptop. As a timing reference I use a Symmetricom XLi.

The equipment is dependent on sampling a finite set of samples after a trigger signal goes high, and also receive azimuth information from an antenna by using two more PFI-lines. The signal is sampled at IF, 30MHz, and the signal is less than 5MHz in bandwidth.

I have now started to look at the Ettus X301, with a GPS OCXO and MXI-express interface, which should be the same as the NI USRP-295xR. It is available as an NI RIO device with three different front-ends, unfortunately none of them working at 30MHz.

Q-1: Ettus has the "BasicRX" front-end, but it is only listed as compatible with the LabVIEW driver, and not necessarily with the RIO. Is the BasicRX front-end usable with the USRP-295XR RIO and MXI-interface together with LabVIEW FPGA? Will I just have to avoid trying to tune the non-existent LO? As long as it is giving me data, I can live with some error messages during configuration...

This is the preferred solution for me, but if absolutely not possible, I have some more questions:

Q-2: The information on the front-ends are really sparse at both NI and Ettus webpages, but the WBX is listed down to 50MHz tuning frequency, having a 40MHz bandwidth low-pass filter at both I and Q. This should mean a total of 80MHz bandwidth with I and Q combined, from -40 to 40MHz. Why is the bandwidth at NI webpages listed as being "40MHz per channel real-time bandwidth" if the low-pass filter of the WBX is 40MHz in both I and Q? Should not the total bandwidth be 80MHz?

Q-3: Assuming a bandwidth from -40 to 40MHz: could I set the WBX LO to 50MHz, get tuned frequencies of the 30MHz signal at 20MHz,  -20MHz, and use a band-pass filter at the FPGA to extract the new signals and suppress the other remainding signals?

Q-4: I have tried to start an FPGA project in LabVIEW, and add the x301/294xR/295xR as a target.The Data clock is locked at 120MHz, which I assume means it will only receive data at 120MS/s IQ? The Ettus x301 is listed as delivering data from the ADC to the FPGA at a rate of 200MS/s, could someone explain to me why the NI USRP RIO is only expecting data at 120MS/s?

[Idara]

Hi again!

I'm replying to my own question, with an update on Q-2 and Q-3.

After searching for more information, I found the schematics of the 40MHz WBX at this link:

http://www.ettus.com/content/files/kb/wbx_schematic.pdf

In the schematics the baseband filter seems to be 20MHz, in contrast to Figure 1 in the following link:

http://www.ettus.com/kb/detail/usrp-bandwidth

I guess I trust the schematics more, and will assume that the bandwidth of the WBX is from -20 to 20 MHz.

I would still like an answer to Q-1 and Q-4, if someone knows?

Best regards from
Idar

[AdeelAnwar]

Idar,

We are also doing a very similar application and using 6540R for IF-signal (43MHz) acquisation based upon Master-Trigger. Similarly ACP/NRP are also being captured using DIO lines. Recently we have also purchsed USRP-RIO so that we may convert our code to USRP-RIO.

USRP WBX board has a filter of 20 MHz on I & Q channel each. This gives a total bandwidth of -20 to 20MHz. This is why NI has written "40 MHz per channel real-time bandwidth" on 294x or 295x devices.

WBX has 50 MHz start frequency and if user wants to get center-frequency lower than 50 MHz, it can be achieved by setting LO-Frequency=50 MHz & Frequency = 30MHz. samp-rate=20MSPS (see Configuration:Advanced:LO Frequency Property for more details). Although this will put ur desired 30 MHz signal at the edge (-20 MHz edge) and signal may not be usable. To overcome this, u may try replacing WBX inside 2940R with WBX-120 from Ettus which has a wider bandwidth -60MHz to 60 MHz.

Using this scheme, u will be able to get the desired 30MHZ signal, but because LO/RF-components of WBX are still involved, u will get the undesired impariaments e.g. DC-offset due to LO-Leakage & IQ-impairements that u were not getting while using 5640R.

Moreover the max-input Rx-signal for WBX is -15 dBm. This may also cause problems because IF-signals are generally amplified (RF>LNA>Mixer>IF) and max-amplitued maybe greater than -15 dBm which may burn WBX LNA.

As i know, currently RIO doesnot support BasixRx but i am myself trying to study the Labview code of USRP-RIO and possibility of making BasixRx compatable with.

Hope this helps,

       Adeel

[Sarah_Y]

Idar, Adeel,

First, let me start by saying this.  We do not honor warranty work if the hardware is not in the shipped configuration.  If you choose to do this and want to eventually re-install the daughterboards that shipped with your unit, please note which slot each daughterboard is installed in.  The correction coefficients stored in the EEPROM are specific to each daughterboard, so installing them in the wrong slot could cause degraded performance.

That said, if you would like to use Basics on your USRP RIO, the attached pdf file has instructions for modifications needed to the sample project to get the Basics up and running.  Note that this is not an officially supported configuration.  Please post back if you find any issues so I can make changes and updates to my documentation.

[Idara]

Hi Adeel,

thank you for your reply!

You cleared up my question regarding the filters! I was thrown a bit off at the Ettus webpage (linked in my second post), where each of the I and Q filters were shown as 40MHz. 

The way you show how to put the IF singal at the edge of the filters would probably not give a satisfying result because of the filter fall-off.

If you find something in the LabVIEW code of the USRP, please keep me informed!

Best regards,

Idar

[Idara]

Hi Sarah.

Thank you for taking the time to put together that PDF and reply to my question!

I believe you show how to use the example project and pre-compiled FPGA bitfile to use the BasixRX and TX front-end cards? If so and they work, that is good news.

I would like to build my own FPGA code for a specific project that I have (radar application), where I need to filter and decimate the received IF signal and then do pulse compression. Should I just be able to exchange the front-end cards, and receive the 120MS/s samples from the ADC's without any huge errors? (without the correction coefficients as you point out in your post)

Best regards from

Idar

[Sarah_Y · Accepted solution]

Hi Idar,

Yes, you should be able to put Basics on your X310/USRP RIO and use LabVIEW FPGA to receive 120 MS/s from the DACs.  The example I posted is actually not for the precompiled bit file.  The example I posted is for LabVIEW FPGA, which allows you to add IP to the FPGA.  There is a sample project that ships with LabVIEW FPGA that is the recommended starting point for building your FGPA application.  The sample project has all of the configuration set up as well as the streaming and buffers/FIFOs in the FGPA  as well as examples for synchronization.  There are comments in the sample code that show where to add your own IP blocks like a filter and decimater that you mentioned.  The pdf I posted shows what changes you need to make to this sample project to use the Basic/LF daughterboards. 

Let me know if I did not explain this clearly or if you have any further questions, I'd be happy to help!

[Sarah_Y]

I wanted to post a follow up to the pdf that I posted (I cannot go back and edit it at this point).  In step 5, I said that the Correct Impairments? control should be set to false.  In addition to setting this to false, false also needs to be saved as the default value.  The other option is to wire a false constant to the Correct Impairments? input on the the Configure Signal.vi on the block diagram of the main VI:

This needs to be done for both instances of Configure Signal.vi.  Attached is also an updated version of the pdf with this correction.

[shabzbd]

Hi Sarah,

Thanks for your pdf that shows to stop the corrections while using the labview FPGA example for the USRP RIOs. Just wanted to know whether the correction coefficients are active if we are using the regular USRP blocks under Instrument IO-> Instrument Drivers->NI-USRP->Tx/Rx blocks such as niUSRP Write Tx Data (poly)/ niUSRP Fetch Rx Data (poly)? If they are active is there a way to switch them off in this mode?

Thanking you loads in advance.

Shabbir A