Can I ping-pong the 2 ADC's in a 2944/x310 to get more bandwidth?

[art_]

There are 2 transceivers in the 294X/x300 series. And there is a parameter 'delay' in the 'ddc parameters' cluster that's fed to the DDC block to, I assume, adjust the timing of the sampling clock. So I can, in theory, split my input signal between the 2 receivers, skew one clock by half a clock period and effectively double my sample rate. I'd have to pipeline any DSP functions on the FPGA to accomodate the split data stream. But if I skew one channels clock how would I then unskew it to line up with the FPGA clock ?

[Victor.F]

Hello Art_

The delay you're referring to is actualy used by the fractionnal decimators and not used to delay the ADC clocks

In the USRP Sample Project designs, you only have access to one common Data Clock on the LV FPGA diagram.

So you cannot use this time-interleave approach.

I've some questions though, to understand what you want to do here

How much BW do you need ?

What do you want to achieve with this?

Thanks

[art_]

Bummer. I'd like at least 200 MHz alias free bandwidth. The more the merrier. I know the 210 MSps ADC has 700 MHz analog bandwidth.