Can I change the HDL for the USRP N210 FPGA to use only I part of data, not I/Q

[mgarey]

Hi all,

While using the USRP N210, we've run into a slight roadblock. We're using UHD's rx_samples_to_file and are able to receive at 20 Msps for 2 minutes using 8-bit complex integer (sc8) over-the-wire format without dropping any samples, but we'd like to receive at a faster data rate, preferably using 16-bit complex integers. We don't really need the Q part of the data, just the I part. So, in addition to using a faster hard drive for the computer and (if we have to) sacrificing half the data bits (using sc8 instead of sc16), we thought about altering the HDL code to only use the I part of the data to help us increase the data rate.

Is this even possible/plausible? How would you suggest going about accomplishing this? Ultimately, our goal is to receive at a faster data rate. Do you have any other ideas? 

Thanks for your input

[Peter_W]

Hi mgarey,

While you may find some other UHD users in these forums who can help the best bet is probably to send your question to support@ettus.com since they are much more experienced in UHD troubleshooting. I don't think you'll be able to edit the FPGA itself but there may be a way to pull back just the I data, I can't say I've tried either one myself though.

Best Regards,

Peter W.

RF PSE

[Peter_W]

Hi mgarey,

While you may find some other UHD users in these forums who can help the best bet is probably to send your question to support@ettus.com since they are much more experienced in UHD troubleshooting. I don't think you'll be able to edit the FPGA itself but there may be a way to pull back just the I data, I can't say I've tried either one myself though.

Best Regards,

Peter W.

RF PSE