can I phase lock 13.56 MHZ signal from external source and generate 13.56 MHZ sine wave from PXI-5404?

[nabhi]

I have a plasma generator running at 13.56 MHz. I wish to generate another signal to be used in the same source but phase locked to the plasma generator signal which is 13.56 MHZ.  I have PXI-5404 card. Can any one suggest how to generate 13.56 MHZ phase locked signal from PXI-5404?  In my application, i wish to generate phase locked signal and then amplify it to some level and inject into another instrument in Plasma physics experiment.

[Raajit_Lall]

Hello Nabhi,

The PLL circuitry divides both the VCXO and the reference clock down to 1 MHz. A phase comparator then compares the two 1 MHz signals and sends out an error signal. This error signal is filtered and sent to the control pin of the VCXO whose frequency gets adjusted. To achieve phase-locked looping correctly, the external reference clock must be a multiple of 1 MHz and should have a frequency error of no more than ±50 ppm. The REF IN connector handles frequencies from 3 MHz to 20 MHz and amplitudes from 250 mV_pk-pk to 5 V_pk-pk.  Therefore, for your case, you can probably use PLL with a multiple of 1 MHz signal, like 13MHz or 14Mhz.

The following figure shows the block diagram for the NI 5404 device PLL circuit.

 

Also refer to :

What are Valid Inputs for Phase-Lock Looping?

Hope that answers your question.

Message Edited by Raajit L on 03-26-2007 12:20 PM

[Raajit_Lall]

Hi Nabhi,

I also wanted to add something else to the above post. A lot of instruments have a 10MHz reference input. If that is the case, then you can use an external 10MHz clock split and feed that into the plasma generator and 5404.  This will ensure that the 13.56MHz sine wave generated by 5404 and plasma generator will be phase-locked.

Hope that helps.

[nabhi]

Thank you very much Raajit.  I have RF generator not RF amplifier for the plasma generator. I have other amplifiers where i can use 13.56 MHZ frequency as reference signal generated from PXI-5404, which i shall try soon. In that case i have to make manual impedence matching network. Where as i have automatic impedance matching built with RF power generator which makes impedence matching very simple.

NI-PXI-5404 is made with DDS IC. IF i use any other dds ic, can i make the PLL which can lock to 13.56 MHZ?
Thanks for the help.
Nabhi

[Raajit_Lall]

Hello Nabhi,

Could you please elaborate a little when you say you want to use other DDS ICs?  How exactly are you going to use this to make the PLL to lock to 13.56MHz.

Thank you,

[nabhi]

Dear Raajit,
    I was thinking of using the DDS ic such as AD9850 from Analog devices and use one dds ic in the loop of PLL. Here DDS is simply a clock source whose freqency will be controlled by error signal generated by independent PLL.
   I am just exploring the possibility, right now i am studying the datasheets of different DDS ics.  for example in AD9850 RF ref in pin i can give 13.56 MHZ and divide by 1 to get same freq in the output. or i can multiply 13.56 by 2 , 3, 4 and give as ref to ref pin of DDS ic and divide the input by corresponding number to get back 13.56 MHZ.
   Some how if i can use PXI-5404 it would be nice.
WHy there is limitation of 1 MHZ steps for using PLL in PXI-5404?
thanks for the help
Nabhiraj