How can I get the CLK OUT using PLL on NI PXI-6652?

[Solanki]

I am try to get the CLK OUT using the source CLK from internal either DDS or PXI_CLK10_IN and PLL to the required frequency. In other words I want the CLK OUT coming from the NI PXI-6652 to be PLL to required frequency.

Ashok

[Kyle_A.]

 Hi Ashok,

What frequency are you trying to PLL to?  Do you have a second signal which you want to PLL your CLK OUT with?  If you generate the DDS Clock on board then it will be generated at your chosen frequency, and PXI_CLK10_IN is a 10MHz chassis controlled signal you can override with the 6652 card. 

[Solanki]

I am trying to PLL 8.192 MHz clock. Yes, I have generated the clock from DDS at chosen frequency. But instead of routing to CLK OUT can I route to PXI_CLK10_IN?

[Kyle_A. · Accepted solution]

Hello,

Unfortunately, there is no direct route in hardware to get the DDS clock to PXI_CLK10_IN.  Typically, PLL is used for external signals which are out of phase with the system, and not for internally generated signals.  Coming from the 665X User Manual online, here is a functional overview of the board:

[Solanki]

I agree that just confirming. So I decided to route the generated DDS clock at chosen frequency to CLK OUT.