SCTL fpga

[Mahesh0459]

I just wanted to check  how it works with 40Mhz defualt clock in  a single cycle timed loop in labview fpga. I generated a sine wave in sctl which runs with 40Mhz SCTL. I took another SCTL which runs with 80Mhz clock n i upconverted signal by interpolating with factor 2. I just want to know that first loop each sample takes 25ns(40Mhz) and 2nd loop each sample takes 12.5ns(80Mhz). How can i do this?? I am attaching my FPGA target pic..

[crossrulz]

That interpolating is likely going to take more than 1 clock cycle to happen, especially at the 80MHz.  You might be able to get away with some pipelining.

[Mahesh0459]

Why it take mora than a clock cycle? we are adding samplles to signal and after filtering out depending on our pass band frequency..

Can u explain more??

Is decimation also takes more than one clock cycle ??