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sbRIO Max DIO frequency

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sbRIO Max DIO frequency

The legacy sbRIO devices have a rated specification for the DIO pins of 10MHz. This is documented in their manuals. Does anyone know the max. frequency on the newer sbRIO 9605/9606 devices RIO mezzanine interface? Their manuals are not yet posted.
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Re: sbRIO Max DIO frequency

Hi,

 

I am also hanging out for the manual for the 9606!

 

But with regards to the max freq of the DIO I would assume it would be very high as the DIO is connected directly to the FPGA and hence would be mostly limited by your program and what type of data you are acquiring.

 

-Adam

Adam Amos | CPE Systems
aamos@cpesys.com.au
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Re: sbRIO Max DIO frequency

Hello all,

 

Glad to see that the new SB-RIOs are so hotly anticipated! Since I don't really know off the top of my head, and I'm not sure if we are fully ready to release that info, I'll have to check around before I can give you an answer.

Cheers!

TJ G
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Re: sbRIO Max DIO frequency

I can take the answer under NDA or restricted circulation as an Alliance member. Confirmation that it's directly tied to the FPGA unlike the existing sbRIO would help too.
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Re: sbRIO Max DIO frequency


SolarSystemsLLC wrote:
I can take the answer under NDA or restricted circulation as an Alliance member. Confirmation that it's directly tied to the FPGA unlike the existing sbRIO would help too.

@SolarSystemsLLC You don’t need an NDA bro, just read the product overview... http://sine.ni.com/nips/cds/view/p/lang/en/nid/210003

 

"Mezzanine Card connector, which is a high-speed, high-bandwidth connector that provides direct access to the processor and 96 3.3 V digital I/O FPGA lines." 



Adam Amos | CPE Systems
aamos@cpesys.com.au
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Re: sbRIO Max DIO frequency

It didn't look like that link lead to the information I'm looking for. What are the signal path impedance, max frequency, termination requirements, etc.? Is the FPGA actually tied to the connector, or is there a buffer in the way?
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Re: sbRIO Max DIO frequency

Hello,

 

The digital I/O on the RMC (RIO Mezzanine Card) connector is directly connected to the FPGA. DIO signals should be routed with 55 ohm characteristic trace impedance to reduce impedance mismatches and unwanted reflections. The FPGA pins are connected to the connector via a 33 Ohm series termination resistor. Since the RMC connector is directly connected to the FPGA, this means that the DIO's frequency is directly related to what you can compile in your FPGA code. More information on this will  become available when the manual is released.

National Instruments
RIO Embedded Hardware PSE

CompactRIO Developers Guide
Solution
Accepted by topic author SolarSystemsLLC
‎08-27-2015 06:09 PM

Re: sbRIO Max DIO frequency

[ Edited ]

Hi SolarSystemsLLC,

 

Please bear with us as we are still working through final edits to the manual before we post it to the web.  As Andrew mentioned in an earlier post the RMC DIO is directly connected to the FPGA through a 33 ohm series termination resistor and the DIO signals are routed with 55ohm characteristic trace impedance.  There is no buffer in line.  In regards to a maximum frequency specification, the DIO capabilities are bounded by the components on a RMC board, signal integrity between the  FPGA and the RMC,  and any application specific timing requirements.  In general, a typical SPI based protocol would be able to close timing with a 10MHz interface rate.  If the applicaiton does not have timing requirements between lines, than you'll likely be able to toggle or sample the lines at a higher rate.  Since the design of RMCs is completely open, the signal integrity and timing for any design should be validated by the designer.

 

I've made a note to update this post when the manual goes live so you'll be aware that its been published.

 

Regards,

 

Steve Bassett

sbRIO-9605/9606 Project Manager

Re: sbRIO Max DIO frequency

Steve,
That's the kind of data I was after, thanks! Are the DIO traces matched length?
Thanks,
Thom
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Re: sbRIO Max DIO frequency

We did take into account trace matching the DIO lines.  Our final documentation will provide a max channel to channel skew number for timing calculations.  

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