sbRIO 9636 FIFO questions

[dr_house82]

Hi everyone,

I'm new to the Realtime/Embedded part of Labview and I'm just starting to play around with the RIO evaluation kit.

I came across a phenomenon that I cannot understand... So maybe it's a stupid thing, so I apologize in advance.

I create a FIFO on the FPGA target (configured to Traget-to-Host DMA) and put 5Million UINT16 values into it from an FPGA loop, as fast as possible. Now, surprisingly, I can read it either with a VI on the realtime chasis, but also with an identical VI situated on the PC host, even with similar performance.

I actually don't understand where the data is buffered and how the PC can access it. I thoght the memory of the DMA-FIFO must be on the RT-target, right? So how does the data come to the PC without a RT-VI? I suppose this method of data transfer (FPGA-to-PC) is not proper use of the FIFO, right?

Moreover, when I check the "Elements remainig" property of the FIFO in the PC-VI or RT-VI, I get numbers around 8000, up to 10000, although the FIFO is configured to have 1023 elements only.

How is this possible?

(Btw.: I do realize that I loose lots of data and the FIFO is to small. Yet, I first want to understand the above points).

The Project is attached as ZIP.

Best regards, and thanks for your efforts,

Joe

[Stephan_D · Accepted solution]

Hey Joe,

NI provides a service which is called NI RIO Server. This service is installed with LabVIEW RealTime on your RealTime target and makes it possible to connect to the FPGA of the cRIO/sbRIO from an computer.

I can't find much information available on the internet, only this page:

How Do I Access RIO devices on a Networked Computer? - National Instruments
http://digital.ni.com/public.nsf/allkb/43F81436B97AEE28862573D40069F440

This is the reasen why you are able to run the same RealTime program on the RIO and the development computer. It is also the reason, why you have to input the IP adresse of the RealTime Target on the program running on the development PC. If you run the VI on the RealTime Taraget itself, it is not necessary to input the IP adresse.

Some information about the FIFO size:

The FIFO is not only one buffer. A FIFO countains two buffers.

One buffer is located in the FPGA itself. It is incredible small (1023 elements by default), but this buffer is ultra fast. The size of this buffer is configurated through the LabVIEW project. You can increase the number of elements in this buffer, but you will never be able to reach a buffer size > 20K elements because of the resource constrains of the FPGA.

The second buffer is located on the RealTime site of the RIO. This buffer can be bigger that the buffer on the FPGA, usually 10x or more. You can configurate the size of the RealTime site buffer through you LabVIEW Code on the RealTime part.

Regards, Stephan

[dr_house82]

Hi Stephan,

great! Thanks a lot for your enlighting answer!

Best regards,

Joachim