cRIO Analog output is not continuous for high speed sampling

[JasperJ]

Ok, thanks for the advise!

It is a sine that is sampled 400 times in one period, so if I want to have a sine with a period of 1 kHz I need a sampling frequency of 400kHz. As the clock of the compactRIO is 40 MHz, AO Rate (ticks) is 40 MHz/400kHz= 100 ticks.

[nanocyte]

The max rate for your card updating just one channel at a time is 3us (pg 14) = 120 ticks minimum.

I reworked your FPGA code a bit to show the pipelining, add some debug, clean some stuff, etc

[JasperJ]

Hi Nanocyte

Thank you for your extensive help the past days. I learned a lot in a short time frame about FPGA and buffers. And I think a lot of people who are struggling with FPGA speed and timing will find a lot of solutions on this forum. As conclusion, if I go to a sine of 300 samples I will be able to generate my 1kHz sine. 😉

Regards

Jasper

[James_McN]

One additional small note on the pipelining:

Normally you would have an additional data valid flag as well. On the first time around your loop there is no valid value for the output phase so it will probably write zero. In this case, it is probably not noticeable anyway (as the module starts at 0V) but a good reference note for the future.