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cRIO Analog output is not continuous for high speed sampling

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Hi Nanocyte

 

Thank you for the nice tips and tricks. I'll adapt my program. I noticed that the modular divide was giving the FPGA a hard time.

 

Regards

Jasper

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@nanocyte wrote:
  • Your use of the i terminal going into that modular divide, eventually you'll hit 2 billion and it won't work any more. You have to come up with a better solution. You can probably turn that while loop into a for loop and then put a while loop around that for loop. This might also get rid of the modular divide which uses a fair amount of resources on the FPGA.

In an FPGA, you will hit that MAXI32 quickly (if a SCTL, ~1.8 minutes).  My solution is to keep a counter in a shift register.  This works better in few ways:

1. Easy to reset with a simple Select

2. You can set the data type to a U8, using less resources

3. Do not have to worry about freezing at the max value of the data type


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@crossrulz wrote:

In an FPGA, you will hit that MAXI32 quickly (if a SCTL, ~1.8 minutes).


 

 Or, in a 100 Hz loop, you'll hit that max in 248 days Smiley Wink

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@nanocyte wrote:

@crossrulz wrote:

In an FPGA, you will hit that MAXI32 quickly (if a SCTL, ~1.8 minutes).


 

 Or, in a 100 Hz loop, you'll hit that max in 248 days Smiley Wink


Ok, I will give you that one.  But the shift register method with the Select does use a lot less fabric.  It has served me well on many projects.


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Hi crossrulz & nanocyte

 

Thank you for your feedback. I was able to adapt my program and it is faster now. I'm still not able to generate a sine of 400 samples with 1kHz, but as I approach the 900 Hz, I find it sufficient. But can you explain to me what is holding up the FPGA?

Also, I think I cannot change 'size' to a U8 representation as its range is 0 to 255 and I will have at least a size of 400.

I solved the race issue by adding a flat sequence and I changed 'teller' to a Boolean (called 'Flag').

 

Thank you for your help!

Jasper

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JasperJ wrote:

I solved the race issue by adding a flat sequence and I changed 'teller' to a Boolean (called 'Flag').


Instead of a flat sequence and local variables, you should just use a shift register for your flag.


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Your code looks pretty good right now. What are you setting for your "AO Rate (ticks)? It might be helpful if you shared your VIs so we can benchmark them. Also, let us know what settings you're using to generate your sine wave.

 

I agree with crossrulz about learning to use shift registers instead of locals. 

 

There is one more small performance tweak you can make. You need to pipeline your AO Write since that's your rate limiting step. Pull the AO Write outside the sequence structure and use either a shift register or a feedback node so that it executes at the beginning of the loop in parallel with all the other processes.

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Hi Nanocyte

 

I agree on the shift register use. It improved the program significantly.

I have added the entire project here. Regarding the pipelining, this looks very promising, but I don't fully understand how to implement it. Should I remove the case structures out of the flat sequence and just put them in the while loop? Where do I add the shift registers/Feedback node?

 

Regards

Jasper

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Hi Nanocyte

 

I watched some tutorials about pipelining and I tried something. Is this a correct way of pipelining? Is it correct to initialize the shift register or should I leave it without initialization? I still see that the loop is to slow as I have a sine of 900 Hz when I ask for a sine of 1 kHz. The input signal is txt-file with a sine sampled with 400 samples. It has one period.

 

Regards

Jasper

 

 

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You have the right idea. Try moving the AO completely out of the sequence structure so that it's right by the left shift register.

 

The shift register can be left initialized or uninitialized. It just depends on what you want that first value to be. If you don't care, then you might as well save a few gates and leave it uninitialized.

 

What are you setting for "AO Rate (ticks)"?

 

 

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