回复： Use the same IO node in sbRIO 9606 (VxWorks) and 9607 (Linux)

[ePower-ahp]

Hi!

I an trying to use same FPGA VI's on both a sbRIO 9612, 9605, 9606 and 9607. For the three first it is no problem as soon as I call the IOs same name on the different boards. For the 9607 I can't get it to work.

An IO node on 9607 looks like:

And the closest I can at a 9606 is:

Because I am not allowed to name it with backslash. 

And it does not works on both targets. 

Is there any other way of doing it than inserting an conditional disable structure for each IO node I use?

Thanks 

Anders

[yayuan]

Hi Anders,

Which version of LabVIEW are you using? And what are other NI software installed? Is it possible to share your project exposing this behavior?

Thanks,

Yan

[ePower-ahp]

Hi!

I am using newest LV version (2015 sp1), with FPGA and RT modules.

Attached is a project showing the probem. in IO.vi I would like to use the same IO node on both targets. 

BR Anders

[yayuan]

One thing to clarify is the sperator (no matter "/" or "\") in the name of those 2 I/O nodse have totally different meanings. For the node on 9607, the "\" in the name is the seperator between the namespace (CLIP) and I/O name, but for the node on 9606, the "/" in the name is the part of the FPGA I/O name. I don't feel reusing this node between 9606 and 9607 is a valid use case. Even there is a tricky way to make them consistent across the targets, I don't know if it will be working as expected on both targets.  So I will suggest you make this piece of code target specific anyway.

Thanks,

Yan

[ePower-ahp]

Hi!

Unfortionately it is not just a small piece os my code I should write different for the different targets, it is a 100 VI fpga project accesing 85 FPGA DIO nodes. The only solution I can see now is to add a conditional disable structure for each access to the DIO, and then use a different node if it is 9612/9605/9606 or it is a 9607 target. 

Else I do not really see a problem in using same code on different targets, off cause I need the design the amount of functions in a single cycle loop to the slowest target. But as I see it, it is one of the main points with LabVIEW, that you can use same code from the fastest FlexRIO system, to the smallest OEM board. 

BR Anders

[DECONN · Accepted solution]

Hi Anders,

I noticed in your example you created a CLIP to interface with your I/O under the 9607. Were you planning on using CLIP specific features? If not, you can simply add an RMC like in the 9606 (right-click 9607 FPGA Target >> New >> RIO Mezzanine Card) and the I/O should look similar. This may give you more parity between targets. Otherwise, I believe the two interfaces will have some different properties. I modified your example project and attached. Take a look at "IO2.vi" and let us know if that is what you were looking for. 

[ePower-ahp]

Hi David!

Super, thanks for your answer, it was the right solution. I thought I had tried the same before without luck, but probably I did something wrong.

Thanks again.

Anders