NI Home
Cart Cart | Help
Hello Events Academic NI Developer Zone Support Solutions Products & Services Contact NI MyNI
You are here: 
NI Home > NI Developer Zone > NI Discussion Forums


Reply
Active Participant
Julien_2831
Posts: 254
0 Kudos
Accepted Solution

Synchronize FPGA clock to RT clock ?

Hello,

 

I use a sbRIO-9612.  Data are acquired for several weeks, and the problem is that the RT clock drifts. I found a technical document for synchronizing an RT clock with SNTP server :

http://digital.ni.com/public.nsf/allkb/F2B057C72B537EA2862572D100646D43?OpenDocument

 

But, I did not found anything about FPGA clock. Since my data are acquired by the FPGA, my question is : how can I synchronize my FPGA clock with my RT clock or SNTP server ?! (it is probably a stupid question, but it explains clearly my problem) Is sbRIO suitable for my need ? Should I give up any "FPGA based acquisition" and use another hardware architecture to perform data acquisition synchronization ?

 

Thank you in advance for any help.

 

Julien

 

Active Participant
Pie56694
Posts: 391

Re: Synchronize FPGA clock to RT clock ?

Hi Julien,

 

Take a look at the "RT Masters FPGA Synchronization Example.vi" on the FPGA Timekeeperpage.  There's a subVI that uses a timed loop to periodically write the current time to the FPGA so that the FPGA can have a synchronized time domain with respect to RT.  If you have questions about that example, try posting them to the Project's Discussion category.

 

- Steve K

 

Active Participant
Julien_2831
Posts: 254
0 Kudos

Re: Synchronize FPGA clock to RT clock ?

Hi Steve,

 

Thank you very much for this very interesting link. That's exactly what I need !

 

Maybe I will have some questions about the library when I try to use it. At the moment, I have just 1 question : password is needed to look at some VI's diagram and I don't particularly want to know all the details, but I'm curious to know which resources are used on FPGA to perform that ?

Active Participant
Pie56694
Posts: 391
0 Kudos

Re: Synchronize FPGA clock to RT clock ?

You can always ask, there's no harm in asking:smileywink:  Post your request to their forum if you haven't already.

 

In general, I've seen NI password protects VIs to A) protect users from internal methods that are undocumented and pose liability concerns if used incorrectly B) protect our value-add intellectual property C) Prevent modifications to code that should not be modified under any circumstances.

 

- Steve K

Active Participant
Julien_2831
Posts: 254
0 Kudos

Re: Synchronize FPGA clock to RT clock ?

Ok many thanks. :smileyhappy:

I've posted my request to the guy who developed it.

Julien

By using this web site, you accept the Terms of Use for this web site. Please read these Terms of Use carefully before using any part of this site. Please go here for information on ni.com's copyright infringement policy.
My Profile | Privacy | Legal | Contact NI © 2011 National Instruments Corporation. All rights reserved.    |    E-Mail this Page E-Mail this Page