07-26-2012 05:11 AM
I use a sbRIO-9612. Data are acquired for several weeks, and the problem is that the RT clock drifts. I found a technical document for synchronizing an RT clock with SNTP server :
But, I did not found anything about FPGA clock. Since my data are acquired by the FPGA, my question is : how can I synchronize my FPGA clock with my RT clock or SNTP server ?! (it is probably a stupid question, but it explains clearly my problem) Is sbRIO suitable for my need ? Should I give up any "FPGA based acquisition" and use another hardware architecture to perform data acquisition synchronization ?
Thank you in advance for any help.
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07-26-2012 08:39 AM
Take a look at the "RT Masters FPGA Synchronization Example.vi" on the FPGA Timekeeperpage. There's a subVI that uses a timed loop to periodically write the current time to the FPGA so that the FPGA can have a synchronized time domain with respect to RT. If you have questions about that example, try posting them to the Project's Discussion category.
- Steve K
07-26-2012 09:16 AM
Thank you very much for this very interesting link. That's exactly what I need !
Maybe I will have some questions about the library when I try to use it. At the moment, I have just 1 question : password is needed to look at some VI's diagram and I don't particularly want to know all the details, but I'm curious to know which resources are used on FPGA to perform that ?
07-26-2012 11:02 AM
You can always ask, there's no harm in asking Post your request to their forum if you haven't already.
In general, I've seen NI password protects VIs to A) protect users from internal methods that are undocumented and pose liability concerns if used incorrectly B) protect our value-add intellectual property C) Prevent modifications to code that should not be modified under any circumstances.
- Steve K