Sine wave generation and real time manipulation for chaos control algorithm

[dannyg]

Brief background:

I am working on implementing a chaos control algorithm for a Duffing oscillator system. In short, I am using LabVIEW and CompactRIO to generate a sine wave (controllable frequency and amplitude) and acquire velocity and displacement data with a vibrometer. Data acquisition must occur at two distinct instances. First, a phase portrait is constructed from continuous displacement and velocity measurements. Then, once per period (anywhere within the period as long as it's consistent; I chose the rising edge for simplicity) a displacement and velocity data point are passed into a separate buffer to generate a Poincare Section.

More importantly, and my area of issue, is that chaos control is model independent and therefore state matrices are constructed from linear regression of perturbed and unperturbed data.

My use case: The attached VI is designed to run for a fixed number of periods (say 100), and after 50 periods a perturbation is made to the sine wave on the rising edge of alternating periods (say 52 54, 56, 58, etc). This perturbation is some scaling of the sine amplitude (2 for simplicity) lasting for some fixed amount of time within a period of excitation. I have attached a screenshot of what I'm aiming for.

My method uses a parallel loop with some boolean conditions to determine period number and rising edge. If true then a for loop executes for a  fixed number of iterations (I've tried while loops with timers for more control but have been unsuccessful). This perturbation is then passed to the generation loop using a target scoped fifo and multipled with the sine wave. While the method works, it seems theres a fixed constant delay from the rising edge in some cases seen with an oscilloscope - the generated sine wave is attached.

Since I'm relatatively new to FPGA I'm not sure how to properly synchronize the perturbation, or what a more effecient technique would be. My thought process was to run a loop that I know will finish before another true condition is reached to prevent any type of significant delay. Note: the perturbation needs to happen in real time because while it is just a constant scaling in the attached VI, each iteration will yield a different amplitude perturbation during actual control which will use a slightly modified version of the attached script. Also in reality (and the eventual goal), the perturbation can be applied anywhere, not necessarily the sine wave amplitude.

Also, I initially had my for loop that writes to the PoincareSection fifo executing just once per rising edge. Unfortunately this generated 1/2 the required number of points (1 measure per period = 100, I was getting a 2x50 array). I changed the iterations to two and get the required number of points but am unsure if 2 iterations are the needed to pass both displacement and velocity, or if im just in essence duplicating the same data (two identical samples at the same period with some larger issue preventing the expected 2x100 array). 

Lastly readability, best practices, and alternative improvements are greatly appreciated even so far as suggestions for a top down rewrite. 

Chassis: NI cRIO-9035

Modules: NI 9263, NI 9221, NI 9234 in slots 1,2 and 3 respectively. 

AO0 and 1 are wired to AI 0 and 1, respectively, and inputs 1 and 2 of NI 9234 are displacement and velocity, respectively.

Thank you!

[Davidvilla87]

Hi,

I am not sure if you are talking about syncronizing the FGPA VI and the host RT VI. If that is the case there are some ways you could use in order to do that. Check this ones:

http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpgaconcepts/pfi_sync/

http://zone.ni.com/reference/en-XX/help/370984R-01/criodevicehelp/usingscanclock/

Also if you go the LabVIEW help > Find examples: you will find a project example using interrupts. The example project is called Interrupts.lvproj

The cRIO develeopers guide is also a good resource. It has a section also where it explains about Synchronizing FPGA and Host VIs Through Interrupts. ( http://www.ni.com/pdf/products/us/fullcriodevguide.pdf )

Hope this helps!

[dannyg]

Thank you for your reply and I will save these links should I encounter snychronization issues between the FPGA and the host. Specifically, my issues arise between the parallel loops both on the FPGA VI. I use a boolean to determine when the generated since wave crossed the rising edge, and this triggers a loop in parallel that runs for a short amount of time (< 1 period). It seems that there's a constant offset added during each iteration that progresses throughout.

Could it perhaps be an issue with FPGA/host communication however the code on the FPGA is functioning as expected as close to real time as possible?

Thank you.

[Davidvilla87]

This boolean is in the RT VI? I believe yes could be something related to the cummunication/synchronization between the FPGA and Host