Sine Generation and data aquisition

[izabela.p]

Hi!
I've created my VIs to generate sine wave and send it to AO and I would like to write my generated signal to file (in future I would like to write signal from AI instead of the generated one). In my opinion it should work, but it doesn't. Please take a look for my VI and tell me, what is wrong.
Thanks!

[MarkCG]

what sepecif parts are working and which ones aren't? All of it?

[izabela.p]

Well. I've attached print screen of front panels fpga vi and host vi. The chart and the graph should show the same signal. AO0 Graph shows signal sent to analog output and Waveform Graph shows signal writted to measurement file. 
And the amplitude... Should be 11V, but it isn't. In fact, I will need lower signal amplitude (about 1Volt), but the signal doesn't generate for amplitudes lower than 11V.

[sprzysta]

Hi Izabela,

If you can please publish your whole project, with that we can look into the code and help you better.

Regards

Sebastian

[izabela.p]

Sure 🙂

[sprzysta]

Hi again,

Firtst thing you should check is the loop rates.

http://www.ni.com/pdf/manuals/373378d.pdf

I you will lok into the specification of your sbRIO than you will se that AO update rate is 336kS/s. So the loop period should be 5us

At your application you set the value of the counbt terminal to 50, it meanscode will execute in 50 top level clock ticks(every tick is 0,025us) so you are overclocking AO.

The same situation is for AI.

Other thing is that you are not able to observe generated signal on the FPGA front PAnel because code executed on FPGA ois just to fast an you see only the latest values in the moment of reading control. My recommendation is to examine output signal with the oscilloscope or AI this will be closer to true.

Try to separate uptading the AO values from the rest of the code, this will allow you to beter manage and debug your code.

 Sine Wave GEnerator should be used in this case inside SCTL. Because every clock tick it will generate one sample. If you will use it with loop that contain other timing source it can cause the effect that you presented to us.

On the host side you need separate file operations and data acquisition, it will be better to put this tasks to parallel loops. Please read about the producer consumer design pattern. File aoperations take long time and can slow down your acquisition.

You are not handling DMA overflow.You are configuring execution time to 10ms but setting sine_wave.Reat timeout to 80ms.

Please be more carefull bout the timing and try to realize it only with one mechanism per loop.

Also 10ms for loop period time can be not stable and cause big jitter for your loop execution(no mather that you are using timed loop). The optimal execution time for loop on windows is 50ms.

Try to consider this problems first

If you will have any problems please ask

Regards

[izabela.p]

Thank you for your answer.
I have made some changes in FPGA VI so far and it works better now. But I don't understand what you exactly mean writting about timed loop because wherever I will put it the vi doesn't activate. Attached file contains printscreen of my new fpga vi.

Now I'm going to think about host Vi, but it seems to be more complicated.

Regards!

Edit: 
When you are talking about producer consument do you mean using gueue and writting data in another loop?

[izabela.p]

I don't know if I should ask this question under this topic but I've started to wonder if it would be good way to generate step signal with amplitude 1V?

[izabela.p]

Hi! 
It's me again

According to your advice I used  Producer/Consument method. I havent' tested it on hardware but I think that it works, but probably I should extend number of elements written to my file depending on signal frequency.

Thank you for your advices 🙂