Rio Target Item Incorrectly Configured

[MyKat]

Hello
cRIO system configuration is :

Main Chassis Target 1 (9082) MXI connected with Target 2 (9159) and Target 2 (9155)
-Created "MXI Test.vi" at Main Chassis (9082) Target 1
-Dragged Mod1/AO0 from Target 1 (9082) to "MXI Test.vi" block diagram
-Dragged Mod1/AI0 from Target 2 (9159) to "MXI Test.vi" block diagram
Mod1/AI0 from Target 2 generates error "FPGA Node item incorrectly configured"
How to reconfigure "Mod1/AI0 from Target 2" properly
NOTE:Please review attached screen shot
Best Regards
MyKat

[ha.nadine]

Has this ever worked?

What have you tried so far?

If I were you, I would try:

• Verifying hardware connections and any indication of the system not working on the hardware (i.e. through status LEDs or similar)
• Checking compatibility and proper installation of drivers & applicable software if this is the first time setting the system up
• Verifying that the devices are showing up as you would expect in NI MAX
• Starting from a new project and seeing if you can add the MXI chassis and I/O Item to the target successfully

[MyKat]

Every thing is properly installed and configured .. can i drag i/o channels from FPGA target to another FPGA Target VI as a explained in the first message ?

Best Regards

MyKat

[ha.nadine]

My apologies, didn't quite understand your question.

No, your FPGA I/O items are target-scoped. This behavior seems expected to me. There are ways to pass data between targets, for example through Peer-to-peer streams. Take a look at the LabVIEW High-Performance FPGA Developer's Guide in the section called Data Transfer Mechanisms (around p.87).

Could you describe your application?

[MyKat]

Hello

Thanks for your reply and support

-My application is reading/writing for c-series modules at three cRIO FPGA Targets,never done it before.

-Have Checked LabVIEW High-Performance FPGA Developer's Guide ,

it's oriented for PXI not cRIO , please advice any LV 2015 example for transferring data between cRIO FPGA targets ? could't found one yet .

-FPGA I/O items are target-scoped ? How to change the items target scope ?

Best Regards

MyKAt

[ha.nadine]

Hi MyKat,

When you say you're reading/writing for c-series modules at three cRIO FPGA targets, what do you mean?

More specifically, what processing are you doing on the first FPGA that requires the second FPGA's resources (for example)? I'm wondering whether each FPGA can act independently and stream data to/from the Real-Time Host or if they really require sharing data directly between each other. To be honest, I'm not sure there would even be a way to do the latter with your system. 

The scope of the I/O items cannot be changed (barring using the Scan Engine and having the I/O Items directly available on the RT Host).

[MyKat]

Hello ,

my cRio MXI system has :

FPGA TARGET > Mod1 > NI 9263 Analog Output module
and
FPGA TARGET 2 > Mod1 > NI 9215 Analog input module

-would like to Create VI under FPGA TARGET > Mod1 > NI 9263 to generate Analog out put corresponding to the Analog input value of FPGA TARGET 2 > Mod1 > NI 9215 Analog input module (ex: Analog Output=0.2 Analog Input)

-How to read FPGA TARGET 2 > Mod1 > NI 9215 Analog input value from the other FPGA TARGET  ?

Please review attached

Best Regards

MyKat

[GreyGrey]

Hi MyKat,

In order to transfer data from one FPGA target to the next, you will have to pass it through the RT layer. I am not aware of a way of passing it directly from one FPGA target to the other when the target involved doesn't support peer-to-peer FIFO's. 

Is there a reason that you can't have those two modules in the same chassis?

[MyKat]

Hello B. Grey

Please review my attached screen shoot , for hight channels count purpose the cRIO system has THREE targets connected via MXI bus  , need to read the c series modules (AI,AO,DIO) betwwen the three FPGA Targets which is a normal demand ,yet could't find any tutorial or Labview example describes how to do it ! please advice?

Best Regards

MyKat

[GreyGrey]

Hi MyKat,

There is a way to pass data from one target to the next, just not directly. You will have to use a Real-Time VI on your cRIO to read data from one FPGA target and then pass the data to the FPGA target that needs it.

This help document goes over a few of the ways that you can communicate from an FPGA target to the host, which in this case would be the Real-Time VI. 

After you have the data in the RT VI, you can use something like the Read/Write Control to then pass that data to the FPGA target that needs it.