Overflowing DMA FIFO for 7966R

[mbothra]

Hi,

I am trying to capture data using the 7966R Flexrio FPGA with 6587 adapter module and transfer it to my PC. I am using the SerDes connector clip.

As suggested in the examples, I have one single cycle timed loop (SCTL) running at Acquired Regional Clock (40MHz, 240 divided by 6) just to capture data and put it into a target scoped FIFO. In another SCTL, I read from that FIFO, do some processing and transfer to DMA FIFO (running at 160 MHz derived clock).

When I try to capture and read data beyond the capacity of my DMA FIFO, it overflows. I tried to reduce the clock for DMA FIFO loop to 60 MHz, but then the FIFO in Acquired Regional Clock overflows. Is there something I am missing ? What is the speed at which I can read off the DMA FIFO ? and why is it that the target scoped FIFO overflows even though the DMA FIFO is running at a faster clock (60MHz) ?

Thanks

[a_clucker]

Hey mbrotha,

I think you are on the right track here – the primary issue is the rates at which you read / write data into / out of the FIFO. So far my understanding is this:

FIFO A:

-Target scoped

-Data written @ 40 MHz

-Data read @ 160 MHz

• Potential for underflow is high, as you are reading much faster than you write. Are you writing multiple points to FIFO A in the 40 MHz loop?

FIFO B:

-DMA…target to host?

-Data written @ 160 MHz

-Data read @ ??? MHz

• Without knowing the read rate, it’s hard to say if the writer is writing too fast or the reader is reading too slow.

I’m slightly confused by the sentence “When I try to capture and read data beyond the capacity of my DMA FIFO, it overflows” – did you mean to say “write”? or “underflows”? Normally you receive an underflow error on read, and an overflow error on write.

The general rule here is that you should match read and write rates (as defined by # points / unit time). If you don’t, you’ll run into either underflow or overflow situations.

Kind Regards,

[mbothra]

Thanks for replying Andrew

FIFO A:

Underflow is taken care of, I don't read when Read timed out is high. I am writing to this FIFO at only one place in the loop.

FIFO B:

I should've mentioned that it is a DMA target to host FIFO.

Data is written at 160 MHz, I don't know the rate at which I am reading on the host side. That was one part of my question, how do I find that out ?

“When I try to capture and read data beyond the capacity of my DMA FIFO, it overflows”  I was trying to say when I read data off the Target to Host DMA FIFO beyond its size, it overflows. Probably it implies that the rate at which host reads is slower than 160MHz ? So to get around that, I decreased FIFO B write speed to 60MHz, but then FIFO A overflowed. I am puzzled by that, theoretically, as long as my read rates are higher than write rates and I am taking care of underflow, I should be able to read an infinite amount of data.

Thanks

Mayank

[a_clucker]

Mayank,

Host side read rate: this can be variable, depending on the host controller operating system, loop rate of the host reading loop, and the number of points you read at a time. A good practice that I see a lot of programmers is the call FIFO Read twice on the host side – the first time, you only care about the Elements Remaining. The second time, you wire the Elements Remaining from the first Read into the Number of Elements input of the second Read function. This way, you’re always trying to read all the elements in the DMA Target to Host FIFO. Try doing this and see if the overflow error stops for FIFO B.

FIFO A overflowing is still a little puzzling – the only think that could be happening is that you are gating when the 160 / 60 MHz loop actually reads from the FIFO based on read timed out. Is it possible that the read is timing out more often then you expect? What is the timeout (and units) on the read for FIFO A?

Thanks,

[mbothra]

Hi Andrew,

I'll try using 'Elements Remaining' output. It should make it more robust. Will let you know how that works.

For FIFO A I am not sure what you mean by "gating when the 160 / 60 MHz loop actually reads from the FIFO based on read timed out." The write to FIFO B is done in a case structure controlled by 'Read Timed Out' output from read operation of FIFO A. 'Read Timeout' of FIFO A is set to 0. See attached NI example picture. My code is very similar to this.

Thanks

Mayank

[muffin.vi]

Mayank,

Could you post a picture of your actual code? (Or attach it to a post?) You shouldn't be having problems with FIFO A overflows based on that example picture you posted, which makes me curious if there's some small detail that's different.

[mbothra]

I am not allowed to post the actual code on a public forum, can I email/PM you ?

[muffin.vi]

Sure, go ahead an PM me!

[mbothra]

Hi,

It turns out flushing the FIFO on the host end and the FPGA end before any new data transfer helps a lot, haven't seen any overflows since I started doing that.

Thanks Andrew and Kyle for you help.

Mayank