Hello everyone,
Does anyone have more information on how the new FPGA Flush (FIFO Method)?
http://zone.ni.com/reference/en-XX/help/372614J-01/lvfpga/fpga_fifo_method/
I would like to know more on how does this flush methed works with the Write method?
I'm hopping this could fix the -50400 buffer error that I get from the FIFO Read method on the Host VI.
Any suggestions or examples are very much appreciated.
Here are some details on the program:
FPGA VI:
Using PCIe-7842, the FPGA VI is supposed to wait for a Top Dead Center (TDC) trigger signal (Channel. 2) then collect data for 42 revolutions:
Time-wise:
At the current engine setting, the Pressure FIFO coming from the FPGA VI should cycle every 1.4 seconds: Engine Running at 1800 RPM = 30 revolutions per seconds Data collected for 42 seconds:
Data Size:
At the end of this 1.4 second, the sample points collected are expected to be 30240 points/elements per FPGA vi Cycle: the CAM signal is set at 720 Pulse per revolution (360 deg/0.5 deg resolution). For 42 revolutions, (720*42). The Pressure FIFO Data as you can see in the flow chart comes from the engine running at 1800 RPM. So, that's 30 revolutions per second and data is collected for 42 seconds
Host VI:
Now, at the Host vi end, the first 2 revolutions are used as a buffer, the data displayed or saved are collected for the remaining 40 revolutions, that's represented by the For (20) loop. That's because the collected data are display/and in 1440 increments instead of 720. We are interested in Engine mechanical cycles that occur every two revolutions, by definitions.
