NI 9401 fpga set line direction method and clock domain other than base clock

[MarkCG]

Hi all,

I have an NI-9401 digital TTL module running on a cRIO-9074 controller and I am doing stuff with this module thorugh an SCTL timed at 80MHz , using a derived clock. Everything is dandy except, how do I change the line direction programmatically with the FPGA method? when I try to do this (set line direction) outside of an SCTL, the compiler complains about trying to access the module from different clock domains. If I do it inside an SCTL, the compiler complains and says that the node can't be executed in 1 cycle. So, damned if you do, damned if you don't. What to do??? Is this maybe possibly a bug?

[NetoNI]

Hello MarkCG, 

Could you tell me more about what do you mean witn the "change the line direction"?

Meanwhile here is a document that has information about SCTL, like the list of functions you can use inside it:

Single-Cycle Timed Loop FAQ for the LabVIEW FPGA Module
http://digital.ni.com/public.nsf/allkb/722A9451AE4E23A586257212007DC5FD?OpenDocument

Feel free to add snips of your code or any information you think could help us have a better understanding of the situation.

Regards

Ernesto

[MarkCG]

Hi Ernesto,

, I made an example project ot demonstrate the issue. Even if not using the set line direction method in an sctl, there should be a way to set it outside the sctl even if clock domains different. 

Mark

[NetoNI]

Hello 

Since you are trying to configure and then read/write, having this within a SCTL could create race conditions. 

Maybe you could add event structures for input and output, just remember to change to read or write according to the situation. Configure it outside the SCTL and then inside the SCRL use the event structures. It is kind of a state machine and you can find more information about it in the following links:

Developing Digital Communication Interfaces with LabVIEW FPGA (Part 1)
http://www.ni.com/white-paper/5385/en/

Developing Digital Communication Interfaces with LabVIEW FPGA (Part 2)
http://www.ni.com/white-paper/5411/en/

Regards.

Ernesto

[MarkCG]

Hi Ernesto,

thanks for the links. I am not doing comms code, I just thought it was strange that I couldn't set the line direction programmatically to output as a setup sort of thing. I know you can the line direction in the project, that is what I am doing now. Not sure how it creates a race condition necesarily, I'll have to check those links. Thank you.

Mark G