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NI 9223 doesn't work at 1MS/s

Dear all,

I have a CRIO-9074 with 3 CRIO modules plugged on it. One of this is NI 9223 which is an analog input working at a maximum sample rate of 1 MS/s. Actually I'm using windows 7 professional 32 bit with Labview professional Development system 2011 (version 11.0.1f2 32 bit) with Real-Time and FPGA. 

 

To test the NI 9223 I simply downloaded the example on NI example finder, I compiled it and I checked that the system is not able to overcame the 110-120 kS/s. If I set a higher sampling rate the sampled voltage value is overwrite before being read. 

 

I decided to modify the program and I put the Generate I/O Sample pulse Method pipelined with Read I/O method in a single while loop. In this way I had still problem with the overwrite beacuse , I guess, Generate I/O and Read I/O are not always executed in the same order. At the end I modified the vi putting in a frame the Read I/O and in a second one the Generate I/O and the FIFO used to collect and send data to the host. In this case the maximum sample rate is around 330 kS/s still far from the nominal 1MS/s. I know that this is not the right architecture but I really don't know why the example doesn't work and I have no idea how to manage this problem in another way.

 

Can you help me in some way?

Thank you 

 

Davide

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Message 1 of 7
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Hi,

 

the problem whit NI 9223 module and the example that you talk about is know. Indeed, there is a CAR - Corrective Action Request - #30724 that deals with the erroneous implementation of the example.

 

To improve the code, the owner of CAR, suggest:

 

Added pipelining loops and removed from FPGA VI to Increase maximum acquisition rate and modified host VI to implement proper DMA FIFO programming practices.

 

I try to implement and improve the code. Bye

 

Mario

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Thank you very much for you help Mario.

 

Let me know if you succed in the improvement of the code

 

Bye

 

Davide

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Message 3 of 7
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I am working with the NI 9223 and have exactly the same problem. I'm pipelining the output of the ADC node into the while loop as described by the first user above. Moreover, I'm checking whether the loop rate (1 MHz because I acquire 1 MS/s) is achieved by using the clock function. In fact it is not, unless I reduce the loop speed by a factor of 3 which corresponds to ~333 kS/s which suggests that the ADC does not provide more than those 333 kS/s at a very low level or hardware level.

 

Any help would be greatly appreciated!

 

 

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If you use the module in User-Controlled I/O Sampling it should work.

 

Why Does User Controlled I/O Sampling Acquire Faster than an I/O Node?

 

There is also an example in Example Finder: NI 9223 User-Controlled IO Sampling.lvproj

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That is a straightforward solution. Thanks so much!

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I tried it and yes it samples at 1 MS/s, but only if I do not write to more than one AO channels of the NI9263 (which is in another cRio slot) simultaneously, Writing to the AO channel is done in parallel while loop, loop rate is 160 kHz. Once I activate analog writing (case around AO node), the acquisition loop slows down and sampling rate does so accordingly.

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