Is it possible to have a multiple FPGA cRIO system?

[Southern_Cross]

I am curios if it's possible to have a single cRIO chassis that can be expanded with additional FPGAs for computations. Meaning, I don't need more I/O but I do have algorithms taking up too much space and need a secondary FPGA to do some parallel processing. Data would be generated in the first FPGA and communicated to the second FPGA where additional processing takes place and then a response/command is sent back to the first FPGA to then be sent out through the I/O. 

I saw something "similar" to this in PXI: http://zone.ni.com/reference/en-XX/help/372831C-01/p2pstreamhelp/p2plv_topo_pipelinefpga/

Althought this solution is dependent upon the PXIe bus it has the general feel for what I'd like. However, I need this in cRIO. Is there a solution that I've missed in my browsing of NI.COM?

It would be OK if the solution consumes one of the cRIO chassis slots.

[crossrulz · Accepted solution]

A cRIO chassis only has 1 FPGA on it.  You may be able to get an expansion chassis and pass the data off to it in order to do the processing.  For what you are talking about, though, you would likely want to add some DIO so that you can directly communicate with the expansion chassis instead of going through the RT and Scan Engine.

Alternatively, get a cRIO that has a bigger FPGA and/or get with your local NI representative to see if you can get some time with an NI systems engineer who can help you optimize your code to fit on a single FPGA.

[Southern_Cross]

Would be nice if NI made a cRIO module that was an additional FPGA. Then, you could just plug it in and be on your way...

[0utlaw]

Have you taken a look at the 9081/9082 with one or more MXI expansion chassis?

http://sine.ni.com/nips/cds/view/p/lang/en/nid/208312

The MXI option should provide quite a bit more bandwidth than an ethernet or similar solution using the scan engine.

Regards,