Highest sampling rate possible for a PID on CRIO

[wqhumems]

Hi, All,

I am trying to build a PID based on the CRIO. I need the sampling rate of the PID to be larger than 50kHz. In other words, one loop of the PID control should be less than 20 microseconds. Does anyone know whether this is possible?

Thanks very much!

[crossrulz]

What modules are you using to read and write your values?  What cRIO chassis are you using?

You should be able to do this.  I suspect you will need to do the PID in the FPGA, but your can try to do the PID calculations in the RT.  So sample that fast, you will need to write your own FPGA (the scan engine is too slow).

[wqhumems]

Hi, crossrulz,

Thanks for your quick reply. I am planning to purchase the cRIO. I am just wondering whether the best controller available can reach this sampling rate. If not, I will find other solutions.

I need to indepedently control the currents in 8 coils, with at least 16 bits resolution. So I guess I will use modules such as NI 9227 to read current value and NI 9265 to output current value.

Thanks,

Wenqi

[crossrulz]

I would go with the 9068 chassis.  It is by far NI's best chassis and uses their Linux RT.  Otherwise, I'm not seeing any major issues.

[AndyClegg]

Good to see that the 9227 has anti-aliasing filters built in. The bandwidth of these should be as appropriate by default - but worth a quick check in the manual.