07-23-2015 10:16 AM
I am trying to optimize a large FPGA VI and was doing some simple tests to determine FPGA usage and timing for some high use items. I was comparing the high throughput divide with the normal one. I am using a cRIO-9066. What I found was that the inputs to the high throughput divide, in this case, appear to be reversed.
The equivalent normal divide works as expected, although it does take more resources and time. Has anyone else seen this? If so, is there a workaround?
Solved! Go to Solution.
07-23-2015 10:55 AM - edited 07-23-2015 10:56 AM
Forgot to add my versions. I am using a fully patched 2014SP1 stack (LabVIEW, FPGA, RIO).
I have also since tested the high throughput divide in pipelined mode, and it has the same issue there, as well.
07-24-2015 09:29 AM
DGrayStratasys,
Try performing a block diagram cleanup on your code. You'll notice that the X control is actually connected to the Y input on the high throughput function, and vise versa.
07-24-2015 09:30 AM
Thanks, that seems to be the theme of most of my problems lately.