FlexRio data delay (generate IO Delay)

[mar_just_one]

Hello Thomas,

I am measuring the delta time at the CB/SCB-2162 board headers using to scope probes.

I would like to consider shorter cables, but before that, it is important for me to know the delay of the front end...maybe just the ballbark.

Regarding my target, I am afraid that 100MHz is just impossible...I dont want to see a signal delayed 2 periods...

regards,

Marwen.

[tcap]

Hello Marwen,

Can you please provide a little more information on your test?
What clock speed is the strobe pin going?
How are you correlating a clock edge to the digital output?

The CLIP has Synchronization Registers, which control the number of clock cycles between when you program a value change and the front end output. You can change this by right clicking the CLIP items in your project and going to Advanced Code Generation. Please note the warnings in the help documentation.

http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpgadialog/fpga_io_advcodegen_db/

The effect of these synchronization registers can be seen in the following article.

http://digital.ni.com/public.nsf/allkb/453B248EC94DC7F98625766B0045DF15

Sadly, I could not find a estimated Front-end Delay, because it depends on the amount of logic and synchronization registers between the signal source and front-end.

Regards,

[mar_just_one]

Hello,

I am trying to implement a slave synchronous digital interface. At every clock edge, the output should change to generate a new bit. This bit will be read from the master side.

As I already described, I am observing the clock and the output data at the end of the VHDCI-VHDCI cable using the headers of an accessory board.

Regarding the IO property option, I am afair that my selected hardware do not offer this possibility.

So you are assuming that there is resynchronization delay in the 25ns total delay? As far as I know, a synchronization register will add a delay of a whole cycle. On the other hand for 1m cable, the round trip delay cannot be less than 10ns. So in best case, there is 15ns delay due to resynchro. 15ns if too much small to be a resynchro delay. I don't think even that in this situation the synthetizer will generate a resynchro registers because the external clock is not sampled, but it is simply used to clock some logic...

Marwen.

[tcap]

Hello Marwen,

The amount of synchronization delay is specified in number of clock cycle. If the clock is slow, this could correspond to the delay to you're seeing.

What is your external clock speed?
If you slow down your clock, does this affect the delay?
Can you please post your project?

Regards,

[mar_just_one]

Hello,

My external clock can vary from 1MHz to 100MHz. I don"t see any variation of the delay when I change the external clock. This prooves maybe that the synchronization delay is a multiple of some internal clock cycles...

Regards,

Marwen.

[tcap]

Hello Marwen,

If you have changed the clock rate with no change, I would expect that this delay is due to hardware propagation.

If you want to look at what is going on inside the CLIP, all of the files are available in the C:\Program Files (x86)\National Instruments\Shared\FlexRIO\IO Modules\NI 6583 directory.

Regards,

[Edmund130]

In Table 7-6 on page # 326 of the Xilinx Virtex 5 Users Manual; it looks like ODELAY only supports Fixed Delay.  So at run time I can only use one FIXED delay per channel for each compiled target, I cannot change this delay in real time, Correct?