01-25-2011 06:00 PM
Hi waiki.wu,
Are you running the FPGA VI on the FPGA target or development computer? You can check this by right-clicking the FPGA Target and looking under "Execute VI on". If it is executing on the computer, it will not compile, which may explain the behavior you are seeing. If you continue to see problems, feel free to post your code.
Regards,
Elizabeth K.
National Instruments | Applications Engineer | www.ni.com/support
01-26-2011 08:48 AM
Hi i am not doing the FPGA target. I am using the RT scan mode on the cRIO, "CompactRIO Scan Mode Tutorial" in the web page. I just did another diagnosis on the VI. I put a probe at the connection before writing into the "Data buffer" variable, and i put a probe at the output of the "Data buffer" in the while loop. There is data writing into the data buffer, but there is no data coming out from the data buffer. The probe window said "Not executed". It seems like the "Data buffer" is empty.
Are these information helpful??
01-26-2011 09:10 AM
I think i got it. I forgot to wire the time out with the constant. and the red clock to the error in of the case structure. Thanks all.
01-26-2011 10:21 AM
I now have another issue. The tdms cannot be found in the c:\. and there is no errors in the error output. Can you help me with that?
01-26-2011 10:41 AM
Which c: are you looking at, the one on the host PC or the one on the crio internal RAM?
01-26-2011 10:43 AM
I was looking at the host pc. I didn't know there is a c: in the internal RAM.
01-26-2011 10:49 AM - edited 01-26-2011 10:49 AM
FTP into the IP address of your CRIO, no username or password unless you set one. That caught me out at first too. You can use windows explorer for it but I'd use an alternative packages as MS implementation of FTP seems to be somewhat poor.
01-26-2011 11:01 AM
Thank you very much. I got it. I am a total newbie to this compactRIO and Labview. Thanks for the help. I really appreciate that.
02-07-2011 02:45 PM
Hi I am trying the FPGA mode this time. Everything works ok until i run it, I got an error after a few lines on the graph. The error code is "-61017", the text is "Open FPGA VI Reference in niLvFpga_Open_cRIO-9118.vi->RT.vi"
Does anyone has similar problem?? I tried to change the loop time and but still it doesn't help.
02-08-2011 11:40 AM
Hi,
First, are you making sure to keep your FPGA VI closed while running your RT VI? Also, it seems like you are able to get to the FIFO.Read portion of the code, which is after the Open FPGA VI Reference. Do you have the Open FPGA VI Reference inside your while loop? Could you post your code?
Regards,
Elizabeth K.
National Instruments | Applications Engineer | www.ni.com/support