02-09-2011 12:12 PM
Hi I have the FPGA vi closed when i run it. However, I can't find the complie option for the FPGA vi when i finish. I am using Labview 2010. I am thinking if this is issue. i don't have open FPGA reference inside the while loop. I have attached the vi to this msg and a shot of the explorer. Sorry for the newbie trouble. I am from building science and I am new to this Labview and compactRIO.
02-09-2011 02:37 PM
Hi, I think i got it working. I think it has sth to do with the complie as the first time i run it it does give me an error. I got it working for now. I tried to change the setup of the 9025 on some channel from RSE to DIFF. however, it will generate the same error i posted. Is that i have to re-complie after i change anything in the hardware setup??
Also, in the scan mode i know how to change the rate at which data is read off the controller. In FPGA mode, how can i change the rate that the data is being read?? thanks
02-10-2011 09:45 AM
Hi, I have attached a screenshort of the output. I have 2 signal wired to 3 and 4, one is 3.3v and one is 5v (from the power supply directly). However, the graph only shows a block of data. Is this normal??
Also, the RT vi will stop execute after a few runs of the data. Is that b/c of the memory of the disk is full?? However, there is no error code showed up.
I am still trying to change the rate the data is sampled and recorded. Can someone point me to the right direction??
02-10-2011 12:29 PM
It looks like you have an "overflow?" method, which is probably what is causing the issue. See if you can increase the size of your fifo, or perhaps slow down the FPGA process which is writing data to the fifo. If it doesn't matter, you can also just ignore the timeout errors. The FPGA will start writing data again when space is available. Finally, you might read data on the RT side in smaller chunks--say 350 elements. If you read 2000 elements, it waits until the FIFO fills up and then tries to pull data out, but if initializing that action on the RT side takes more time than it takes to fill the fifo up to the max on the FPGA side, it will overflow and stop the RT vi.
With regards to the chart, it seems like you are selecting only a certain block of data and sending that to the chart. Since it is a chart, it should retain data from previous iterations of the loop, so that is likely why you are seeing blocks of data because of that array modification.
02-10-2011 02:13 PM
Hi, i have change the elements and other parameters. However, i can't still get the data that i want. All i need is a continuous line of the data respect to time, in sec. I have attached the output that i can get. If i set the "count" to 100000uSec and the time out at 1000mSec, i get this graph. If i set bigger number to the count it will give me at Read FPGA error. If i change the time out in the FIFO, it will give me a overflow error. I try to read help regarding the properties of the FPGA read/write control for the "count" and the time out in the FIFO read. however, i am not still very sure what is the effect for this particular example.
02-11-2011 10:23 AM - edited 02-11-2011 10:24 AM
It looks like your realtime loop is moving too fast. Why don't you give this example a try:
or you could try one of the examples in the example finder (tools>>find examples>>toolkits and modules>>FPGA...)
Then, if that gets the result you want for one channel, you can look at what that example is doing and learn from it.
02-15-2011 09:00 AM
I am using an NI9205, NI 9401, and NI9263 and cRIO-9074 and I have been trying to log data into the disk. When I set the properties of the FPGA FIFO to the "data type= FXP" and "word length of 26 bits" and "integer length of 5" (see the screenshot) my program fails to log meaningful data. For example for an encoder I will get only values of 0, 15.9999952 and -16.
However when I change the data type to "I16", I am able to record meanningful data.
Any ideas on why my system is behaving like this?
BTW, I am using Labview 8.6. Please let me know if you need more info.
02-15-2011 09:19 AM
Sorry I forgot to attach the screenshot for the FIFO properties.
By the way, I have attached a screenshot for my system configuration from MAX. As can be seen the NI RIO 3.0.1 is installed on my cRIO, but my host PC has NI 3.0. Could this be a potential problem? Another dumb question is that how come under the NI RIO 3.0.1 tree, I can see a NI RIO 3.0.0?
Sorry for my ignorance as I was given this system and I was not invloved in installing this software or drivers.
02-16-2011 04:23 PM
What datatype are you writing into the FIFO on the FPGA? I would start by looking for a datatype mis-match at either the RT or FPGA side of the FIFO.
02-16-2011 07:24 PM
Thanks very much for your reply. I did have a mismatch! On my FPGA side I was writing two types of fixed point and integer to the FIFO and on the RT side the data type was double precision.
I changed it now to make sure that on both sides, I have FXP data type (see attached!, is it correct?) but then now I am getting an Error while TDMS attempts to write. I have attached the error here.