08-12-2014 01:37 PM
I am using a DMA to pass data up and down between my FPGA and my RT (cRIO). I made the DMA data type a U64. My intent was to use 16 bits for a command ID, another 16 bits for a signal ID, and then make the lower 32 bits the data. My data is supposed to be passed around as a SGL and then converted into the Fixed-Point inside of the FPGA (which I was told was more efficient). The problem I have ran into is that I have no way to type cast the SGL into a U32 to then be joined with my message.
I did manage to make an IP node based on the example given here. But that just seems like a kludge to me. There has got be be a better way. Anybody know of a better way? All I really want is to reinterpret the bits as a U32.
08-12-2014 01:49 PM - edited 08-12-2014 01:50 PM
I've only done this with the VHDL provided by Dragis here: http://forums.ni.com/t5/LabVIEW/Flatten-floating-point-on-FPGA-for-multichannel-DMA/m-p/2576179#M776...
While it's slightly different HDL, it's the exact same thing you're trying to avoid here...
To the best of my knowledge, it's not a language feature available on the palettes anywhere. I also don't see it on the idea exchange yet.
08-12-2014 02:30 PM
@T-REX$ wrote:
I also don't see it on the idea exchange yet.
09-22-2014 07:08 AM
I needed U32 to typecset to SGL type DMA channel.
I had to created this IP code:
https://decibel.ni.com/content/docs/DOC-26569
you needed same only in opposite way
I am working for your Idea
09-22-2014 07:30 AM
Yeah, we did find that one as well. We went with the code by Dragis since it was written to be a little more generic. Still not happy that we have to go with an IP node for something that should take 0 gates.
11-27-2015 04:35 AM - edited 11-27-2015 04:36 AM
Hi, Having the same issue, I've found this archived note ( Using Fixed-Point Data Types with Integer-Based IP in LabVIEW FPGA 8.5.x and 8.6.x ).
I think this may less kludge.
11-29-2015 04:57 PM
@El-MDA wrote:
Hi, Having the same issue, I've found this archived note ( Using Fixed-Point Data Types with Integer-Based IP in LabVIEW FPGA 8.5.x and 8.6.x ).
I think this may less kludge.
The problem with that is that you have to coerce the SGL to a FXP. I wanted to put my SGL directly into my message, which was a U64 sent over a DMA FIFO.