ERROR:HDLCompiler:69

[BillTür]

Hello

I am trying to compile some code for a FPGA on a FlexRIO 7965R. This works fine for default clock rate (40 MHz).

I would like to use a higher rate though but in that case a compilation error occurs:

ERROR:HDLCompiler:69 - "\NIFPGA\jobs\IgEJ5Z6_rYTw6YC\Interface.vhd" Line 172: <rioclk40derived15x2d00mhzfifowsignalcountportfromreshold> is not declared.
ERROR:HDLCompiler:69 - "\NIFPGA\jobs\IgEJ5Z6_rYTw6YC\Interface.vhd" Line 173: <rioclk40derived15x2d00mhzfifowsignalcountportfromreshold> is not declared.
ERROR:HDLCompiler:69 - "\NIFPGA\jobs\IgEJ5Z6_rYTw6YC\Interface.vhd" Line 174: <rioclk40derived15x2d00mhzfifowsignalcountporttoreshold> is not declared.
ERROR:HDLCompiler:69 - "\NIFPGA\jobs\IgEJ5Z6_rYTw6YC\Interface.vhd" Line 175: <rioclk40derived15x2d00mhzfifowsignalcountporttoreshold> is not declared.

I have searched the forums for this problem and it seems people solved the issue by switching the decimal sign in Windows. This didn't help though.

Some are claiming, they had to rebuild the project, that didn't help either.

Any suggestions?

I hope I made my problem clear but feel free to ask questions.

I am using LabVIEW 2011

Thank you!

[BillTür · Accepted solution]

OK, it is now compiling the code without errors. The trick is to set a different top-level clock in the FPGA project - properties of FPGA target.

Sorry for wasting anybody's time!

[subbu708]

Hi...!!!

I am also having the same problem,what u are faced previously. I am not undestanding how you have solved this problem.It is really irritating me.I have surfed the web for this.Please clarify the above.....Now iam working on Atlys Evalution board.I am working on DDR implementation for the same.

Thanks .....!! In advance.

--

Subbu

[BillTür]

Hi subbu,

can you explain what you are trying to do?

From the name of the board, I suspect it is not programmed in LabView? Which program are you using to program the board?

[avik_airbus]

Hello Bill,

         I am also getting a similar error...

ERROR:HDLCompiler:69 - "/opt/apps/NIFPGA/jobs/OMy92oI_Zo5Sh3y/Interface.vhd" Line 193: <rioclk40outputwstreamwfifocountportfromreshold> is not declared.

In my FPGA VI I am using two single cycle timed loops: one at 120MHz (sample clock) and the other at 40MHz (onboard clock)...

      May I know what could be the reason, and what you did to fix it??

With best regards,

S. Kumar Raja

[BillTür]

Hi, did you derive the sample clock from the onboard clock or do you have an IO clock? Try setting the default clock rate of the FPGA to 120 MHz and set the other SCTL to 40 MHz (you can set your default clock by right-clicking the FPGA target -> Properties -> Top-Level-Clock and then select a previoulsy configured clock. You can set clocks by right-clicking the 40 MHz onboard clock -> New FPGA Derived Clock).

[avik_airbus]

Thanks for your reply...

   The sample clock of 120MHz used in my FPGA needs to be enabled using the 40MHz

onboard clock.. For this purpose, a specific VI is given in the host side.. Perhaps, for this

reason, labivew FPGA does not allow the sample clock to be the top-level clock.. I saw

the below message in the Top-level clock configuration window.

"LabVIEW FPGA does not support external clocks or clocks that support and require runtime enable/disable as top-level clocks."

   One of the loops in the FPGA must run at the sample clock of 120MHz... As you suggested,

I am trying out the following. I derived a separate 120MHz clock from the default 40MHz

onboard clock, and set this "new 120MHz" clock as the top-level clock.   I have initiated the

compilation with a hope it works...

                           I will keep you updated..

With best regards,

S. Kumar Raja

[avik_airbus]

Nope... It did not work. The compilation reported the same error...

Any other suggestions??

       I am wondering if a Block-memory based FIFO can be used across two clock

domains: one 40MHz onboard clock and a sample clock of 120MHz....

With best regards,

S. Kumar Raja

[BillTür]

FIFOs should be useable across clock domains without problems as long as arbitration is disabled if i remember correctly.

Can you tell me which module you are using running at 120 MHz? Do you have an IO Module Clock set up? How are the clocks in the IO Module settings setup? Do you set the clock with a constant/control wired to the timed loop or do you use the settings window (I dont't think it matters, just trying to rule things out)?

You could try to use the 120 MHz clock for both SCTLs and use a counter to only execute code every third iteration in the SCTL where you want to have 40 MHz. This is not the solution we are looking for but it might resolve the issue temporarily...

[Dragis]

BillTur, have you filed a bug report on this issue? If not, please do so. LabVIEW FPGA should give you helpful errors about any unsupported features before getting these errors from the Xilinx tools. 

Unfortunately, I'm not set up at the moment to help debug those clocking issues. 

The FIFOs  using Block Ram should support Read and Write methods in different clock domains. The arbitration doesn't come into play unless you have multiple calls to individual methods (e.g. multiple calls to the Read method).