Decrease NI 5791 ADC/DAC sample rate

[Yue_123]

 Hello all, I am using  NI 5791 and want to decrease the ADC/DAC sampling rate from 130MHz to a lower rate. I am a little confused about whether it is possible, since the manual says the ADC/DAC works "AT" 130MHz, but it also says the clock distribution IC AD9511 is programmable. So if the output (ADC/DAC sample clock) of AD9511 is programmable, doesn't that mean ADC/DAC can work at any clock rate? And if it can, how to program the AD9511 (I searched online, but there is no clue at all)?

Any help is appreciated.

[Blizzard]

Hello Yue,

If you want to slow down your sample rate using FPGA, the best option is to use the Loop Timer Express VI. If you place this VI in the first frame of a flat sequence structure, it will force the rest of your loop to run at the rate specified in your loop timer. I've included more information about the loop timer below:

Manage Exectution Rates with FPGA Timing Functions (FPGA Module): http://zone.ni.com/reference/en-XX/help/371599J-01/lvfpgaconcepts/using_timing_functions/

I hope this helps!

Regards,

Anna L

[BauerPower]

Hi!

On the 5791, the only way to change the clock output from the AD9511 would be to change the clock source to use CLK IN and use an external clock. You could do this by using a Timing and Sync module (or some other clock source) to generate your new sample clock and then connect that to the CLK IN BNC connector on the front of the 5791. From there, you can select CLK IN as the clock source in LabVIEW. I would recommend taking a look at the 579X sample project that you can access by clicking "Create Project" on the LabVIEW splash screen.

If using an external clock is not an option, you will have to manually decimate your incoming IQ data on the FPGA. You could do this by only reading the data on specific iterations of your Single Cycle Timed Loop. As an example, your SCTL will be running at either IIO Module\Data Clock or IO Module\Data Clock x2. If you are using IO Module\Data Clock of 130MHz, then you will be sampling every 130MHz with no decimation. If instead, you use a case structure with an alternating boolean flag to govern when you acquire, you could read at every other iteration of IO Mod Clock, sampling at 65MHz. If you need to sample at a frequency of say 4/5 x 130MHz =108MHz, you could have some other logic to  read the IO Node four out of every five iterations.

Does this help answer your question?