Configuring IO delay in NI 6587 for Data Acquisition

[mbothra]

Hi,

I am trying to read LVDS data using 6587 adapter module with 7966R FPGA module. The external clock I receive looks identical to data (just hi-lo toggling). In order to capture the data I need to shift the phase of the clock by a quarter clock cycle to get the most stable data values. Since the clock IDELAY is not accessible (always set to 0) I am thinking of shifting all my data accordingly. I have some questions on how to use DATA_IDELAY_INCREMENT for this purpose.

a) Logic high level on DATA_IDELAY_INCREMENT increases data delay by one tap per ACQ_REGIONAL_CLOCK, where one tap is 78.125ps nominally, so what should I do to get a delay of  400ps ? Is it related to number of rising edges on DATA_IDELAY_INCREMENT ?

b) How can I use IDELAY_CALIBRATION_CLOCK ?

[diabeticdaniel · Accepted solution]

mbothra,

To answer your first question, you would need to have a configuration loop that sets the DATA_IDELAY_INCREMENT to true for as many clock ticks as you need to reach 400 ps. The DATA_IDELAY_INCREMENT node sets the enable input of the IODELAY Xilinx primitive to true, and the direction of the IODELAY is hard-coded to always increment. What this means is that for every clock tick where the DATA_IDELAY_INCREMENT node is true, the delay will increase by 78.125 ps.

In your case, you would need 400/78.125 clock ticks, or 5.12 (rounded either down to 5 clock ticks for a delay of 390.625 ps or up to 6 clock ticks for a delay of 468.75 ps). To implement this, you could have a single cycle timed loop run for the number of iterations you need, stop the loop, then start your actual data acquisition loops.

For your second question, the IDELAY_CALIBRATION_CLOCK is locked at 200 MHz. There are no changes that you can make to this value to cause any kind of delay.

[mbothra]

Thanks !!