Can a CRIO system have only one host VI, one FPGA VI, and no RT VI?

[DowNow_]

Hi,

We have an application that requires only a host VI and FPGA VI, but we are using CRIO rather than R-Series, etc. to get a higher channel density. It's working good early on, but I just wanted to check with you all to see if we're going to run into problems becasue we have no .rtexe or RT VI in our system. Thanks.

-cc

[crossrulz]

Short answer: No, you have to have an RT application.

In my last few cRIO applications, all I used the RT for was passing data between the FPGA and the host.  But I added some other features like storing the latest settings sent to the FPGA in a configuration file (this allowed the controllers to be truely headless).

[DowNow_]

Hi,

Thanks for your reply. I'm able to load the FPGA bitfile and operate the FPGA VI from my host VI using Open FPGA VI Reference, and Read/Write Control from the FPGA Interface palette. I've also used Invoke Method to successfully Wait on IRQ and Acknlowledge IRQ. I should say I'm on a sbRIO-9631 (Eval Kit) and I'm going to use a cRIO-9067.

So right now, it's working for me without an RT application. Though there is a .rtexe file on the sbRIO and I have dip 4 NO APP set. I don't have a headless app, what I'm doing always requires a host VI. Maybe I need the long answer, is there a specific error, crash, or bug I'm going to run into, like, hmm, I don't know, bad DMA FIFO performance or something? Thanks again.

cc

[Miro_T]

It is not necessary to run a RT VI, your system can consist of only host and FPGA VIs. However, when you choose to run all of your code on the host you are losing determinism in your system. You are not able to time-bound execution times as you would be on the RT. Running code on RT also enables you to run at lot higher execution rates compare to host. You are also loosing option to run your sbRIO headless since your code resides on the host.  

It really comes down to what your application needs and what is your final goal with it. If your application does not require a deterministic bound-time execution, running higher rates then (~1kHz) or ability to run headless then you can continue to run your code on the host only.

[DowNow_]

Hi,

Thanks for your post. All the determinisim in our app resides on the FPGA. We could make this a headless app, but there's always going to be a PC host sitting there and running. The RT VI would add complexity for the same functionality, and there's some desire to simplify the system in the interest of long-term maintenance. I'm just double checking to make sure the design is ok.

cc

[James_McN]

Hi,

I've run systems like this in the past and not run into issues. I'm fairly sure this is what the NI ethernet RIO chassis do anyway so would expect it to be production ready.

Cheers,
James