Bits missed during real time acquisition and saving tdms file

[incisive]

Hi

I am using FLEXRIO Ni 6587 adaptor module, PXIe- 7962R Labview FPGA. and 8135 controller. I am acquiring reat time data (8 bits) at 50MHz internal clock on 6587 ddc lvds port. From those 8 bits I choose 2 bits among them and save multiple files of 100MB tdms file using write to measurement file express VI. I am able to acquire data from FPGA. I have kept the depth of DMA fifo to 65535.

 On host PC, I kept the following settings.

Host Depth (to avoid overflow)= 50M

Timeout=5000

Elements to write=65535.

The issue is when data comes in real time, there is no overflow, I am able to save multiple files. but I miss few bits in between. In order to verify that, I acquired a 100 bit continuous pattern and compared the files. A number of bits are missed in between. at 3 instances within one file. What can be the reason? I am attaching the my VIs. please help. 

How do you calculate the loop time of host VI? Do I have to work on clock edges? If yes,then how to use negative edge since data generates on positive edge.

Also kindly let me know, I have made a matlab program for depuncturing and viterbi decoding on matlab. Can I use that in mathscript within labview? Is vitdec function supported?

Thanks in advance.

[TheXiadow]

You should not need to set a loop time for the host VI. Usually, you just set a fixed number of elements to read, and the host will read that many elements off of the FIFO as they become available. 

Section 4 of the following resource illustrates this:

http://www.ni.com/tutorial/4534/en/

[incisive]

How to acquire data on negative edge of the clock? Can anyone please explain in detail.

[a_clucker]

Hi,

In your first post, you mentioned calculating host loop times, then immediately mention positive and negative edges. For your last question (how to acquire data on negative edge) do you mean acquiring data on the FPGA from the actual I/O, or do you mean acquiring data from the FIFO on the real-time side?

As for calculating loop time, you can do this by getting the tick count of a current loop iteration and subtracting it from the tick count from the last iteration. Here is a Community Example that shows the basic programming structure to do this.

[incisive]

That's because I was able to calculate the host loop timing. 

By negative edge i meant acquiring data on negative edge of clock of FPGA using external clock from actual IO port.

[scotia673]

If I understand what you're looking for, "NI 6587 Finite Acquisition - External Clock Start Trigger (FPGA).vi" might help point you in the right direction. You'd be limited to a 500Mz clock speed if you're using the basic CLIP; it would be ideal if you were using the SERDES CLIP. Which are you using?

[incisive]

i am currently using The basic connector. Due to certain reason(hardware issue) i can't use the differential clock. i am using external single ended SMA clock in. My clock is 50MHZ. the program i am using is high throughput streaming where you save data in tdms in the end.
The problem is I Am getting sampling errors as the file size increases more than 100MB. Either the reason can be the clock or DMA FIFO read sample size adjustment.
so firstly i would like to know how to use negative edge?

[Daniel.Parrott]

So is your desired sample rate 50 MHz? You'll be fine at 50 MHz, but you can't use the falling edge to drive the FPGA. 

It also looks like the problem is throughput to the host and not in the FPGA. I would look at the High Throughput Streaming example to find some ways to improve your input. 

What are the exact error's you're getting?