128 channel acquisition on sbRIO-9612

[Julien_31]

Hello all,

My question doesn't deal with a precise technical issue, but I begin to wonder if I'm trying to do something really adapted to sbRIO functionalities.

Here is my equipment :

- sbRIO-9612 (32 AI ; system memory 128 MB ; processor speed 400 Mhz ; spartan 3 prodided with 46080 logic cells and 720 kbits embedded RAM)

- 3 extension modules 9205 (3*32 AI)

Here is what I'm supposed to do :

- 128 channel acquisition with sbRIO-9612, at 2 kHz per channel. These channels correspond to current and voltage measurements.

- Power calculation for almost 128 channels (lower than 2 kHz rate, since each power calculation is performed with a certain amount of points)

- For intellectual property reasons, I can't explain all the details on this forum but I have to process those 128 channel data in order to extract many others informations

Here is what I wanted to do :

- using 1 DMA FIFO to transfer current and voltage data to RT controller

- using 1 DMA FIFO to transfer power data to RT controller

- using 1 DMA FIFO to transfer others data

- since only 3 DMA FIFO are available on sbRIO, I plan to use an array command on FPGA VI front panel to retrieve scale parameters (given by RT controller) : no way to use a LUT for scaling because scale parameters can change depending on our sensor references (1 single sensor = 1 reference)

- since only 3 DMA FIFO are available on sbRIO, I plan to use another array command on FPGA VI front panel to specify others parameters (given by RT controller) : for example, I need to know for each current channel which voltage channel is associated to it (for power calculation)

NB : maybe I could use only 1 array instead of 2 arrays to transfer all the parameters given by RT controller, I've not tried yet but I guess that there's no reason for it to improve significantly compilation results.

Here is what I've already done (please see screenshots attached) :

- I started from "cRIO waveform library" FPGA VI for doing acquisition : now it is modified since I need more channels (I also removed the shift register which was used to pipeline data : my problem at the moment is not relevant to timing considerations but it has something to do with the amount of FPGA logic cells used)

- I've added a power calculation subVI (I'm using BRAMs)

- 2 array commands (size : 128 items) are placed on the FPGA VI front panel (data type is : FXP +/-16;12 for scale parameters and U8 for tension/current couple parameters)

Here are the results :

- When I run compilation, "total slices" was more than 99% (data scaling was not even done, array command was just put on the front panel and it was not linked yet in the diagram !) : I'm not surprised of course, with these 2 big arrays on the front panel ! I've not tried but if I perform data scaling, compilation will not even go to the end.

- If I use 64 channels instead of 128 (data scaling is done now), than "total slices" is 78%...and I'm not optimistic because even if I accept the fact of using only 64 channels, I will have to code others algorithms (or at least, I will need to call VHDL code, but I guess it doesn't make a big difference). For information, those algorithms can't be run by RT code with many channels because of speed capability, so it must be done on FPGA chipset.

Hope my explanation is clear...So my questions are : do you think FPGA target (or at least sbRIO 9612) is done for such a kind of use ? Do you have any comment about what I'm trying to do ? (there are restrictions with RT processor capabilities but my question is mainly about the using of the FPGA resources)

Thank you for any answer,

J.

[reddog]

Since the 9205 is a multiplexed module, you might want to experiment with using the IO Sample method to acquire and store a single channel of data at a time rather than using the I/O Node to acquire and store all 32 channels at once.  As you have things structured now, you'll have to store and route 128 fxp values in the FPGA fabric at once.  If you go with the IO sample method, you should be able reduce this to 4 fxp values.  Programming the acquisition in this manner is more complicated than just using the I/O Node, but it sounds like it might be worth the effort in your case.  If you're not familiar with the IO Sample method, you can find it by dropping the FPGA I/O Method Node and configuring the 9205 as the target item.  Once you've done that, you should be able to click on the node to see the methods supported by the module (of which the IO Sample method is one of them).  You'll probably want to check out the help for this method to fully understand how it works.  You can also look at the example project that ships with the module for this method.  It should be located at <LV Dir>\examples\CompactRIO\Module Specific\NI 9205\NI 9205 Advanced IO\NI 9205 Advanced IO.lvproj.  I'm not sure if this will completely get you over the hump space wise, but it should help.

[Julien_31]

Thank you very much for this interesting suggestion.

I'm going to read carefully the documents I've found about IO Sample Method, but can you please explain to me the idea of that technique in a few words ?

[Julien_31]

That's OK I begin to understand how it works. Maybe I will have some others questions later but it's OK at the moment. Thank you very much again reddog ! (and if anybody has any other suggestion, don't hesitate) 🙂