VST Synchronization: Ok with RFSG, Problem with RFSA

[serge_malo]

Hi all,

We are trying to synchronize 2 VSTs (5644) with NI RFSA and NI RFSG.

So far, we have been able to synchronize the RF Transmission of the 2 VST with RFSG, down a difference below 100ps. This is excellent!

But we haven't been able to repeat this success with RFSA: we have time differences in the order of 100us between the 2 VST.

We think that we are following all the indications of the RFSA documentation, as indicated here:
http://zone.ni.com/reference/en-XX/help/372058N-01/vstdevices/5644_rfsa_gsynchronizing_clock_signals...
We even make sure buffers are empty at the beginning of the acquisition by manually emptying the VST buffers before call RFSAInitiate.

NOTES:

Our application is coded in C++ only.

We do not and cannot share the LOs between the 2 VSTs, because we need to Rx/Tx at different frequencies.

Does anybody have a suggestion of what we could try?
We attached the NI I/O Trace of our acquisition. Please, let us know if you see something wrong.

We are using RFSA 14.5
PXIe-8135 Controller, Win7 x64
PXIe-1075 Chassis.
PXIe-5644R in slot #2 and #6

Best regards,
Serge

[Bumblebee_Tuna]

Hi Serge,

Could you further describe how you are using the 2 VSTs as well as how you are setting up the synchronization in your program?

[serge_malo]

Hello,

We are using the 2 VSTs with the FPGA bit streams that we got from a NI example, we haven't changed anything in the LabVIEW FPGA code.
(NI Streaming Host Example for the NI PXIe-5644R, its a NI LabVIEW 2014 example). Bit stream file is "c:\Users\Public\Documents\National Instruments\FPGA Extensions Bitfiles\NI PXIe-5644R\NI Streaming for VST.lvbitx"

We are using 5MSPS sampling rate.
We are using the same external 10MHz ref clock, splitted for the 2 VSTs, connected on each Front Panel's Ref IN.

You can find the detailed setting up of the synchronization in the NI IO trace file included in my first post.

Let me know if need addtional information.

Regards,
Serge

[serge_malo]

Hi again,

Please, let me know if I should open a regular "ticket" through NI e-mail support.

Best regards,

Serge

[Bumblebee_Tuna]

Hi Serge,

The advantage of opening a service request is that an Applications Engineer will be dedicated to work on the issue. The community is a good avenue for brainstorming from various sources but given this particular post hasn't received much attention a service request would be a good next step. If you are able to, update this community page with a resolution when you come to one. 

-J

[serge_malo · Accepted solution]

Hi all,

Finally, Support (Kevin Sooch) helped us to fix the issue:

In order to have a sub nano-second sync between 2 VST recording channels, we had to change 2 things in our application:

1) When using direct calls to the FPGA, such as "NiFpga_ReadFifoU32", you will need to manually empty the Streaming buffer by calling NiFpga_ReadFifoU32 until the buffer is empty, before starting the acquisition. Otherwise, you could have old samples left in the VST buffers, and they are probably not same amount for both VST.

2) When setting the Digital Edge trigger for your recording, use the following command:

  niRFSA_ConfigureDigitalEdgeStartTrigger(m_rfsa_session, NIRFSA_VAL_SYNC_START_TRIGGER_STR, NIRFSA_VAL_RISING_EDGE);

  DO NOT USE THIS SEQUENCE:

  niRFSA_SetAttributeViInt32(m_rfsa_session, 0, NIRFSA_ATTR_START_TRIGGER_TYPE, NIRFSA_VAL_DIGITAL_EDGE);

  niRFSA_SetAttributeViString(m_rfsa_session, 0, NIRFSA_ATTR_DIGITAL_EDGE_START_TRIGGER_SOURCE, NIRFSA_VAL_PXI_TRIG0_STR);

We now have sync levels in the order ot 250ps.

Thanks to all for your help!

[shawn.t]

Hi Serge,

Was there something about using the set attribute calls that was not working, or was it just that the start trigger needed to be NIRFSA_VAL_SYNC_START_TRIGGER_STR?