VST NI 5646R Error -52018

[Rodéric_L]

Hello,

I (lightly) modified the High Throughput Streaming example for the NI 5644R so it could run on the NI 5646R. Everything was working fine, I then launched an RFSA example from NI (RFSA Acquire Continuous IQ). It seems to have messed up the FPGA because I now get error -52018 every time I launch my VI. RFSA and RFSG examples seem to work just fine.

This error is described here: http://www.ni.com/product-documentation/14254/en/

It has been a known issue for at least 3 years now, I doubt NI intends to fix it. I don't understand how I am supposed to "Ensure that the SCTL clocks are running before calling the VI that returns the error", in the code I explicitely declare the RF IO loop to run on Data Clock

Best Regards

[Rodéric_L]

I don't know why, but doing an output reset solved the issue... But it didn't last long, I run the RFSA example again and now I get error -61046... It says that I should configure my external clock but I don't use one

[shawn.t]

Hi Roderic,

Can you share the version of RFSA, VST runtime, and VST IDLs that you're using? Also, it would be nice to understand the modifications that you made to the streaming example.

From the errors, it sounds like the clocks are having a hard time getting configured. Note that the only clock that is guaranteed to be running when you load an FPGA image is the 40 MHz clock. The data clock is started by the basecard configure clocks VI, and this must be run before any communication is attempted using any clock but the 40 MHz clock. Otherwise, the communication will time out. This is likely what's causing both errors.

A good way to check if the clocks are running is to add a counter within an SCTL based off of each clock. Read the counter through a register in a 40 MHz based SCTL and wire that to a front panel indicator. You can read this from the host, and if it is increasing, then the clock is operational.

[Rodéric_L]

NI PXI platform Services Runtime 15.0
NI RFSA and RFSG 15.0
LabVIEW 2015
NI VST IDL version: I don't have this information from MAX

The major things I had to do is change the way data is acquired, the IO nodes return arrays instead of scalar values
I also had to change a few things in the FPGA (I had to dig and found a comment in a sub VI saying that the input
should be an array for NI 5646R and scalar for NI 5644R, only the scalar version seemed to be implemented so I don't see
how the code is supposed to be compatible for both cards)

I oversimplified the Host VI, it seems that the FPGA needs some parameters from the host to run properly, the problem
is some of the init VIs are not compatible with the NI 5646R (Reg bus VIs)

[shawn.t]

Those changes seem pretty benign. I wonder if your hardware is in need of repair. If you power down the chassis completely, power back up, and then only run RFSA examples will you still get an error? If you do, then that points to the hardware only locking to its reference intermittently. If you only begin getting the error once you've run the streaming code, then you can focus on that.

[Rodéric_L · Accepted solution]

It seems that things are working way better with another example I got. The example can be generated from the project window (create a new VST project for the 5646R) it was not easy to find but it runs smoothly! (the init phase seems to be improved but I didn't have time to dig much further)

Thank you for your help shawn