Tim,
The hardware comparison is supported only on the 655x devices and does not support serial triggering. The hardware compare works by downloading a known response pattern which is used to make a sample by sample comparison. You can think of this pattern like a normal dynamic generation task where each sample of the response is compared on each clock cycle. For serial triggering, you need a state machine to compare the same sample until it matches then compare the next, if it matches then compare the next, if it doesn't match then go back to the first. This sort of serial triggering is not supported in hardware.
One thing you may could try is to have a shift register perform a serial to parallel conversion. The parallel width would be the size of your start trigger pattern. If you capture all of those parallel lines on your device but only pay attention to the MSB then the serial word would be parallel which you could use a pattern match trigger that would be synchronous to the first sample. This burns a lot of channels but may be easier to implement than a CPLD.
