Hello josephkirmani,
The NI-5781 allows for analog input up to 100 MS/s (14-bit) and analog output of up 100 MS/s (16-bit). In the FPGA portion of your FlexRIO application, you will need to place the input\output FPGA I\O Nodes in a Single Cycle Timed Loop (SCTL). Each iteration of the SCTL must execute within one clock cycle of the IO Module Clock. By default, IO Module Clock is 100 MHz and is sourced from the NI 5781 CLIP. At a very basic level, this setup will force the FAM to sample\output a value every 1us. Thus, that would be your datarate.
You could correlate the data rate of the inputs\outputs of your FAM based on the rate of the SCTL loop as long FPGA code is built correctly. However, I do not believe there is a way, in software, to verify data rate directly. I would recommend taking a look at the LabVIEW example finder and searching for the following three examples:
NI 5781 – Clock Select.lvproj
NI 5781 – Getting Started.lvproj
NI 5781 AO with Clock Division.lvproj
Alternatively, you could use an oscilloscope to verify if the outputted waveform is output at the frequency you specified in the code.
Best Regards,
j_bou
