Re : data delay for acquisition

[alex34070]

Hi everybody,

I am using a PXIe-6548 board to send datas to a FPGA and then acquiring the results. I use HSDIO 2.0.

I have problem to acquire the right datas, the efpa has an internal delay according to its application (adder, inverter, shift  register, etc.) and I think this delay may distrub the measure (in high frequency).

I've tried to use data delay but I don't really know which value I have to put there. Especially that I'm sweeping the frequency -> Does the delay value has to change or it has to remain constant? 

I'm not sure if I have to put the data delay on the acquisition, generation or the clock.

Another thing which can be be disturbing my measures is that among the generated data there is the clock use by the FPGA to calculate the output (which I try to acquire properly).

Please find a part of my VI attached,

Thanks in advance,

Alexandre

[alex34070]

I think I might need a data delay greater than 100%.

I found this help : http://digital.ni.com/public.nsf/allkb/53BFD784329FF5BD86257210005D2004?OpenDocument

But I don't know how to make the 2:1 interpolation, is there any help for this?

Thanks in advance

Alex