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configuring delays pxi 6561
Timothy 123
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10-11-2006 04:23 PM
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I have a pxi 6561 for testing asics. I want to setup the aquisition
clock and the system clock used for the generation channel to have a
delay between each other. I am doing this by a slightly modified hsdio
example. The original example is Dynamic Generation and
Acquisition-Source Synchronous.vi. In order to establish a delay the
system clock is exported into clk out terminals and then a wire is used
to wire this to the strobe terminals. The variable stream delay is the
variable that is used to determine the delay in between the aquisition
and system clock. I was wondering whether in this approach the system
clock is delayed is as well by the same amount, canceling out the whole
effect to make the delay 0, becuase I have observed no change in my
aquired waveforms with changes in the delay setting. Also the delay
setting is set by a property node before the signal is exported. See my
vi below if it helps to clarify this issue.
Ryan_M
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10-11-2006 04:47 PM
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Timothy,
I don't see where in the attached code you are adjusting the delays and I think I"m a bit confused about your application. Please correct me if I'm wrong but I think your intent is to have the generation and acquisition sessions running at the same frequency but with an offset between each other? IE, signal acquired 2ns after generation, for example.
Have you tried using the same clock source (CLKIN or OnBoard) as your clock source for both sessions and use the data delay feature to introduce the offset? Data Delay (and exported clock delay) gives you the ability to introduce a delay between when the clock arrives and when it actually samples the data. For generation, it introduces delay between the exported sample clock and the data (allowing for adjusted setup and hold times for instance). Delays can be added to the data or clock for generation or to the data on acquisition. Refer to the specifications for the 6562, there are some limitations when using this delay feature relative to frequency of operation.
There are some examples that ship with LabVIEW that use this data delay (and exported clock delay) feature.
I don't see where in the attached code you are adjusting the delays and I think I"m a bit confused about your application. Please correct me if I'm wrong but I think your intent is to have the generation and acquisition sessions running at the same frequency but with an offset between each other? IE, signal acquired 2ns after generation, for example.
Have you tried using the same clock source (CLKIN or OnBoard) as your clock source for both sessions and use the data delay feature to introduce the offset? Data Delay (and exported clock delay) gives you the ability to introduce a delay between when the clock arrives and when it actually samples the data. For generation, it introduces delay between the exported sample clock and the data (allowing for adjusted setup and hold times for instance). Delays can be added to the data or clock for generation or to the data on acquisition. Refer to the specifications for the 6562, there are some limitations when using this delay feature relative to frequency of operation.
There are some examples that ship with LabVIEW that use this data delay (and exported clock delay) feature.
