Understanding how to set up and use a FlexRIO sample clock

[JKSH]

Hello,

Following this discussion on glitching inputs, I've learnt that I need to use the Sample Clock domain for reading AI Nodes in my NI 5734. So, I right clicked "FPGA Target" -> "New FPGA Base Clock" and selected "IO Module Clock 0". In general, I followed instructions at http://www.ni.com/pdf/manuals/375653a.pdf

Questions:

1. I noticed that, no matter what value I put in "Compile for single frequency", timed loops that use this clock run at 120 MHz. Is this expected?
2. I want to acquire at 10 MHz, not 120 MHz. Is there a way to create a Derived Clock from the Sample Clock? (Right-clicking on the clock doesn't give me the "New FPGA Derived Clock" option)
3. In the FIDL example, Acq Engine on 5734 PXIe-7962R.lvproj, "IO Module Clock 0" is configured to compile for "100 MHz" instead of 120 MHz. Is there any significance behind this value? (From #1, I gather that the value is ignored)
4. In the sample code below, I get "Error -61046 occurred at Read/Write Control" unless I exclude the "Reset" node from the host VI. This issue does not occur if I use the 40 MHz Onboard Clock instead of IO Module Clock 0 (although I would get glitched data). Have I misconfigured something?
1. In my actual, more complex program, I get the same error even with the node disabled, if I stop and restart the host VI -- but the next attempt would succeed.
2. I've attached the sample project file, VIs and bitfile, in case they're useful.

[Matthew-B · Accepted solution]

Hi FKSH,

You are correct that you need to access your I/O on the NI 5734 in the sample clock domain:

(this information is in the LabVIEW Help for the NI 5734 CLIP)

This will be either IO Module Clock 0 or Sample Clock based on your version of the FlexRIO driver you have installed. Based on your snippets, it looks like you're using LabVIEW 2014, so be sure to have FlexRIO 14.0 or FlexRIO 14.1 installed. If you have FlexRIO 14.0 or earlier, the sample clock will be IO Module Clock 0. If you have FlexRIO 14.1 or later, this will be Sample Clock:

(also from the NI 5734 CLIP documentation in the help)

The only supported sampling rate is 120 MHz unless you use an external clock on CLK IN and it needs to be between 50 MHz and 120 MHz (see page 9 of the manual). If you want to acquire at 10 MHz, the easiest thing to do would be to sample the I/O at 120 MHz and then decimate the data by a factor of 12 (i.e. keep every 12 data points only and throw the rest away).

With regards to FIDL, I'm guessing you're referring to the configuration in the clock properties:

This configuration doesn't actually change the frequency of the clock. The compiler uses this value to ensure that the logic can operate at the specified frequency, but the actual clock is provided elsewhere (in this case, it comes from the FAM).

Finally, I've seen error -61046 happen most often due to internal clock configurations. Double check that you're using the right clock as the single-cycle timed loop source as I mentioned above. In general, I don't recommend writing directly to an indicator at 120 MHz as there is a lot of other logic that needs to happen in order for it to update the indicator. The data is sent to a different clock domain under the hood so you can actually update the data and I'm suspecting that there are some conflicts with the clocks. You'll also miss data as the host won't be able to read all the data before it gets overwritten. Instead, I would use DMA FIFOs if you need all the data you acquire or to send the data to a different loop which will be responsible for updating the indicator in a slower clock domain.

In general, I always recommend the getting started examples in the Example Finder as a good place to check if the hardware is working correctly and as a reference for proper configuration. Once you compile the code, you should be able to run it out of the box to acquire some data. These examples will be under Hardware Input and Output»FlexRIO»IO Modules»NI 573X»NI 5734.

Best Regards,

[BauerPower]

What Matt said is spot on.

One addition that I'd make is that you will probably want to use a decimation filter in order to avoid the significant aliasing distortion that you could get from downsampling. There are a few ways to implement this but I'd recommend taking a look at the FIR Compiler VI  You can design the decimation filter using the Digital Filter Design toolkit and then export those coefficients to a .coe file which is readable by the XIlinx FIR Compiler. The Multirate filter might look something like this.

Wish I had more time but I've got to run, hope this helps!

[BauerPower]

Double Tap

[JKSH]

@Matt,

Thank you so much for your detailed explanations and links to reading material. It really clarified some uncertainties I had. I've since realized that a lot of my uncertainties could have been avoided if I had read the documentation more carefully, so thank you for your patience and wiillingness to help!

Regarding Error -61046, I believe it occurred here because I didn't wait for the FPGA to finish initialization before trying to drive it. I dropped Host API Tools.lvlib:Host Wait for IO Module Initialization Done.vi into my block diagram, and the error disappeared.

Yes, I currently have FlexRIO 14.0 installed. I looked through the FlexRIO 14.1 changelog and didn't see anything I really need, so I think I'll wait for the Developer Suite DVDs to arrive before upgrading. 😄

@Rob,

Great tip, thanks. I was originally going to simply grab every 12th sample, but an anti-aliasing filter is definitely a good idea.