01-29-2015 05:52 PM
So PFI acquisition is always started before data acquisition, causing the PFI FIFO to start filling before the data FIFO. I did a quick test to see what kind of delay to expect between writes, and the delay varied between 100 to 500 clock cycles, depending on the receiving clock frequency.
I agree with Kyle. The portion of your code seen in teh attached control_IO_start.png file is a likely culprit.
One possible solution could be to use a single start control placed in the processing loop. This would be connected to a register. The register would then be read in both PFI and acquisition clock domains. A bit slip would then be used with a test pattern to align the data (to correct for the clock divider uncertainty).
The distributed_start_register.png shows what this may look like. You may not even not to mess with the bit slip depending on how slow your signal is.
01-30-2015 12:17 AM
David-A, could you help me and get your solution as file (in my VI)?
01-30-2015 12:45 PM
Here is the VI I made to create the screenshot from the last post.
01-31-2015 06:17 AM
@David-A wrote:
Here is the VI I made to create the screenshot from the last post.
Could save the VI in 2011 version?
02-02-2015 12:19 AM
Now I found that registers does not supported in LabView 2011. How we can solve problem using proposed solution?
02-02-2015 10:04 AM
You can use a local or global variable to accomplish the same thing since they can also be read by multiple readers from different clock domains. If you take a look at the High Performance LabVIEW FPGA Develoers Guide it has an entire chapter about data transfer mechanisms. Page 81 even has a handy table that tells you which ones are suitable for clock domain crossing and multiple readers.
02-08-2015 02:25 AM - edited 02-08-2015 02:42 AM
02-10-2015 04:33 PM
Can you post your code that used local variables to distribute a trigger between clock domains? Was the data alignment better, worse, no difference?
Using you're current method of streaming the data from the two seperate clock domains into a single clock domain will allow you to align the data. To align the data you need to identify when they should all see a falling edge, and delay whichever set of signals is ahead by the desired number of clock cycles.
02-12-2015 06:27 AM - edited 02-12-2015 06:28 AM
I attached project with variables. Data alignment when i use variables - no difference. The result - http://forums.ni.com/ni/attachments/ni/270/14421/2/1.png
03-12-2015 11:59 AM