Synchronous acquisition on PXI-7962 (NI 6587)

[David-A]

---

So PFI acquisition is always started before data acquisition, causing the PFI FIFO to start filling before the data FIFO.  I did a quick test to see what kind of delay to expect between writes, and the delay varied between 100 to 500 clock cycles, depending on the receiving clock frequency. 

---

I agree with Kyle. The portion of your code seen in teh attached control_IO_start.png file is a likely culprit.

---

One possible solution could be to use a single start control placed in the processing loop. This would be connected to a register. The register would then be read in both PFI and acquisition clock domains. A bit slip would then be used with a test pattern to align the data (to correct for the clock divider uncertainty).

---

The distributed_start_register.png shows what this may look like. You may not even not to mess with the bit slip depending on how slow your signal is.

[Valentin87]

David-A, could you help me and get your solution as file (in my VI)?

[David-A]

Here is the VI I made to create the screenshot from the last post. 

[Valentin87]

---

@David-A wrote:

Here is the VI I made to create the screenshot from the last post. 

---

Could save the VI in 2011 version?

[Valentin87]

Now I found that registers does not supported in LabView 2011. How we can solve problem using proposed solution?

[David-A]

You can use a local or global variable to accomplish the same thing since they can also be read by multiple readers from different clock domains. If you take a look at the High Performance LabVIEW FPGA Develoers Guide it has an entire chapter about data transfer mechanisms. Page 81 even has a handy table that tells you which ones are suitable for clock domain crossing and multiple readers.

[Valentin87]

Local variables didn't help. I simplify project but it doesn't work again.

 

[David-A]

Can you post your code that used local variables to distribute a trigger between clock domains? Was the data alignment better, worse, no difference?

Using you're current method of streaming the data from the two seperate clock domains into a single clock domain will allow you to align the data. To align the data you need to identify when they should all see a falling edge, and delay whichever set of signals is ahead by the desired number of clock cycles.

[Valentin87]

 I attached project with variables. Data alignment when i use variables - no difference. The result - http://forums.ni.com/ni/attachments/ni/270/14421/2/1.png

[incisive]

hi
I have a PXI 7962R fpga and ni 6587 adapter module. I want to use external clock to implement a simple adder xilinx Ip core. I input the IO clock 0 an external clock of 20 MHz with 3 V pk to pk. I then attached it to single cycle timed loop and fpga clock enable VI and implemented my IP core inside the loop. I did not use the fpga disable vi since i want continuous running vi.
now the project complied but on place and route i didnt see any other clock except for the main 40 MHz implemented. Upon completion of compilation i received an error that fpga and host could not communicate. either the clock z not connected or is nott generated according to specifications. what might be the problem?