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Synchronous acquisition on PXI-7962 (NI 6587)

I have PXIe-7962 with adapter module NI 6587. Where I can find examples where commit synchronous acquisition on data (lvds) and pfi channels at the same time? Please help. Thanks.

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Message 1 of 21
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The FlexRIO Development Library doesn't have examples specific to the NI 6587. But, it does have synchronization examples that you can use as a starting point and then modify to suit your needs. And, it's a great starting point generally speaking.

 

They're also 4 LabVIEW shipping examples featuring the NI 6587, which you can access by going to Help>>Find Examples... and then seraching "6587".

 

Could you elaborate more on your application? What're the data rates of your two input signals? What degree of synchronization do you require?

 

Any additional information you can provide will be helpful in allowing others to give you relevant guidance.

 

Mike

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I don't have any examples. But assuming you are talking about the LVDS Data and the LVDS PFI if you set the clock source used by each regional clock to the same source you should see the LVDS PFI and LVDS Data output aligned data from their respective IO Nodes. In practice you might see that the data is misaligned by a sample. If this complication does arise you could initialize with a test pattern and ratchet up the IDELAYs on one of them until you see the test pattern coming out of the two aligned. 

 

Capture.PNG

 

Message 3 of 21
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Hi!

 

When you say synchronous acquisiton do you mean source synchronous acquisiton or synchronization between channels / IO modules? Are you using an external reference clock? You should be able to start with one of the examples that Mike mentioned, such as the "NI 6587 Finite Acquisition - External Clock Start Trigger (FPGA).vi" If you are using an external data clock you can then select Strobe Bypass for the IO clock source on the front panel to ensure that the 6587 uses an external clock. 

 

From there, I would do what David recommended. During configuration, you would also want to make sure that you set all PFI lines to read by wiring a 0 to the PFI write enable nodes. Are you using LVDS PFI lines or SE?

 

If you provide us with some more specifics on what you are trying to do we may be able to give you better suggestions.

 

Best Regards,

Rob

 

Rob B
FlexRIO Product Manager
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I would also highly recommend taking a look at the CLIP help for the 6587 in the LabVIEW Help, it has detailed descriptions of every signal for each CLIP. You can access that by going to LV Help and then searching "6587."

Rob B
FlexRIO Product Manager
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I try to explain what do I mean.

 

I have a board NI SMA-2164 and NI SMA-2165. With PXIe-7962 and NI6585 I generate custom data. For this I use project from examples for NI 6585 Continuous Generation DDR - Internal Clock. Data generates in DDR mode and count up.

 

Then I connected data from NI 6585 to NI 6587 as follows:

NI 6585 -->  NI 6587

  DIO0            DIO0

  DIO1            DIO1

  DIO2            DIO2

  DIO3            DIO3

  DIO4            PFI1

  DIO5            PFI2

 

And then I use my project to receive data. This project I attached. As a result I get next picture (1.png in attached files).

And we can see any delay from acquired data from PFI channels to LVDS channels. Sometimes that delay =0. But more often not =0. Why does that delay appear?

 

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What's interesting is that in the project you attached the PFI lines are ahead by two clock edges, and in the image you posted the PFI lines are behind by two clock edges. 

 

Have you tried using the IDELAYs to see if the lines that are ahead a few clock ticks can be aligned with the lines that are behind? 

 

idelay.PNG

 

Also, does the alignment change during acquisition? When the generation starts and stops? Or only on power up?

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Message 7 of 21
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@David-A wrote:

What's interesting is that in the project you attached the PFI lines are ahead by two clock edges, and in the image you posted the PFI lines are behind by two clock edges. 

 

Have you tried using the IDELAYs to see if the lines that are ahead a few clock ticks can be aligned with the lines that are behind? 

 

idelay.PNG

 

Also, does the alignment change during acquisition? When the generation starts and stops? Or only on power up?


Now I try use Idelay. The result is the same. The delay is exists. The delay not constant: sometimes behind by two clock edges, sometimes behind by one clock edges, sometimes matches.

 

The generation is always on. I acquire data at random moment of time.

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Due to the complexity of this issue and if you're able, please go to http://www.ni.com/support/ and create a service request to contact your local branch for additional assistance.

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There's a couple issues that are probably occuring with the code, and they aren't very obvious.  First, read/write control nodes are always executed from the top control down.  So PFI acquisition is always started before data acquisition, causing the PFI FIFO to start filling before the data FIFO.  I did a quick test to see what kind of delay to expect between writes, and the delay varied between 100 to 500 clock cycles, depending on the receiving clock frequency.

 

The second issue is that there is a possibility that the clock dividers for both PFI and data are coming up in different phases.  This can cause the deserializers to output a different window of samples than another phase.

 

One possible solution could be to use a single start control placed in the processing loop. This would be connected to a register. The register would then be read in both PFI and acquisition clock domains. A bit slip would then be used with a test pattern to align the data (to correct for the clock divider uncertainty).

 

Another solution could be to constantly pipe all data into the processing loop from the regional clock loops. From there, a test pattern could be used along with the CLIP's bit slip to align the PFI and data. A single start control can then be used to start piping data into the DMA FIFOs.

 

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