PXIe Clock Distribution

[egghead]

I had a technical question regarding the clock distribution per the PXI-5 Hardware Spec Rev 1.0. The spec seems to state that the backplane is to provide two 100MHz clocks (PXIe_CLK100 & PXIe_SYNC100) and one 10MHz clock (PXI_CLK10) to each PXI peripheral slot. I have no peripheral slots in my design, but I am using four hybrid slots, one timing slot and one system slot. As the backplane, would I also need to provide the two 100MHz clocks and one 10MHz clock to these slots as well? Also, I noticed that the system slot pin out has the pins that would normally be used for PXIe_CLK100 & PXIe_SYNC100 as RSV status and what seems to be a yREFCLK+- for each y-Link. So are these REFCLKs outputs from the system module? In other words, it seems, from the pin out, that the system module generates its own REFCLKs, is this true? Could someone please point me to a simple block diagram of the PXI-5 clock distribution?

[Krista H]

This is a duplicate post please refer to this link for more information.

[Spencer S.]

The questions on the PXI Express clocking are answered in section 4.4 of the PXI Express specification.  Please review that section and let us know if you still have questions.  The questions on the PCI Express reference clocks are covered in the CompactPCI Express specification.  Please review the sections on the PCI Express reference clock and let us know if you have further questions.